UPSD3422_06 Datasheet, PDF (40/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

8032 addressing modes
uPSD34xx
adding either the 16-bit PC or DPTR value to the contents of the accumulator. The value in
the accumulator is referred to as an index. The data fetched from the final location in
program memory is stored into the accumulator, overwriting the index value that was
previously stored there. For example:
MOVC A, @A+DPTR
; Move code byte relative to
; DPTR into accumulator
MOVC A, @A+PC
; Move code byte relative to PC
; into accumulator
9.8
Relative Addressing
This mode will add the two’s-compliment number stored in the second byte of the instruction
to the program counter for short jumps within +128 or –127 addresses relative to the
program counter. This is commonly used for looping and is very efficient since no additional
bus cycle is needed to fetch the jump destination address. For example:
SJMP 34h
; Jump 34h bytes ahead (in program
; memory) of the address at which
; the SJMP instruction is stored. If
; SJMP is at 1000h, program
; execution jumps to 1034h.
9.9
Absolute Addressing
This mode will append the 5 high-order bits of the address of the next instruction to the 11
low-order bits of an ACALL or AJUMP instruction to produce a 16-bit jump address. The
jump will be within the same 2K byte page of program memory as the first byte of the
following instruction. For example:
AJMP 0500h
; If next instruction is located at
; address 4000h, the resulting jump
; will be made to 4500h.
9.10
Long Addressing
This mode will use the 16-bits contained in the two bytes following the instruction byte as a
jump destination address for LCALL and LJMP instructions. For example:
LJMP 0500h
; Unconditionally jump to address
; 0500h in program memory
9.11
Bit Addressing
This mode allows setting or clearing an individual bit without disturbing the other bits within
an 8-bit value of internal SRAM. Bit Addressing is only available for certain locations in 8032
DATA and SFR memory. Valid locations are DATA addresses 20h - 2Fh and for SFR
addresses whose base address ends with 0h or 8h. (Example: The SFR, IE, has a base
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