UPSD3422_06 Datasheet, PDF (217/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

uPSD34xx
PSD module
Figure 75. DPLD Logic Array
PLD INPUT BUS
8032 ADDRESS (A0 - A15)
16
8032 CNTL (RD, WR, PSEN, ALE) 4
PSM MODULE RESET (RST)
1
POWER-DOWN INDICATOR (PDN) 1
PIN INPUT PORTS A, B, C (IMCs) 20
PIN INPUT PORT D
2
PAGE REGISTER (PGR0 - PGR7) 8
OMC FEEDBACK (MCELLAB.FB0-7) 8
OMC FEEDBACK (MCELLBC.FB0-7) 8
FLASH MEM PROG STATUS (RDYBSY) 1
NUMBER OF
PRODUCT TERMS
3
FS0
3
FS1
3
FS2
3
FS3
3
FS4
3
FS5
3
FS6
3
FS7
3
CSBOOT0
3
CSBOOT1
3
CSBOOT2
3
CSBOOT3
MAIN
FLASH
MEMORY
SECTOR
SELECTS
SECONDARY
FLASH
MEMORY
SECTOR
SELECTS
AI06601A
2
RS0
SRAM
SELECT
I/O & CONTROL
1
CSIOP
REGISTERS
SELECT
1
ECS0
EXTERNAL
CHIP-
1
ECS1
SELECTS
(PORT D)
1
PSEL0
PERIPHERAL
I/O MODE
1
PSEL1
RANGE
SELECTS
28.5.27
General PLD (GPLD)
The GPLD is used to create general system logic. Figure 74 on page 215 shows the
architecture of the entire GPLD, and Figure 76 on page 218 shows the relationship between
one OMC, one IMC, and one I/O port pin, which is representative of pins on Ports A, B, and
C. It is important to understand how these elements work together. A more detailed
description will follow for the three major blocks (OMC, IMC, I/O Port) shown in Figure 76.
Figure 76 also shows which csiop registers to access for various PLD and I/O functions.
The GPLD contains:
● 16 Output Macrocells (OMC)
● 20 Input Macrocells (IMC)
● OMC Allocator
● Product Term Allocator inside each OMC
● AND-OR Array capable of generating up to 137 product terms
● Three I/O Ports, A, B, and C
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