UPSD3422_06 Datasheet, PDF (125/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

uPSD34xx
I²C interface
23.12
I²C START sample setting (S1SETUP)
The S1SETUP register (Table 59) determines how many times an I²C bus START condition
will be sampled before the SIOE validates the START condition, giving the SIOE the ability
to reject noise or illegal transmissions.
Because the minimum duration of an START condition varies with I²C bus speed (f_SCL), and
also because the uPSD34xx may be operated with a wide variety of frequencies (f_OSC), it is
necessary to scale the number of samples per START condition based on f_OSC and f_SCL.
In Slave mode, the SIOE recognizes the beginning of a START condition when it detects a
'1'-to-'0' transition on the SDA bus line while the SCL line is high (see Figure 42 on
page 117). The SIOE must then validate the START condition by sampling the bus lines to
ensure SDA remains low and SCL remains high for a minimum amount of hold time,
t_HLDSTA. Once validated, the SIOE begins receiving the address byte that follows the START
condition.
If the EN_SS Bit (in the S1SETUP Register) is not set, then the SIOE will sample only once
after detecting the '1'-to-'0' transition on SDA. This single sample is taken 1/f_OSC seconds
after the initial 1-to-0 transition was detected. However, more samples should be taken to
ensure there is a valid START condition.
To take more samples, the SIOE should be initialized such that the EN_SS Bit is set, and a
value is written to the SMPL_SET[6:0] field of the S1SETUP Register to specify how many
samples to take. The goal is to take a good number of samples during the minimum START
condition hold time, t_HLDSTA, but no so many samples that the bus will be sampled after
t_HLDSTA expires.
Table 60 on page 126 describes the relationship between the contents of S1SETUP and the
resulting number of I²C bus samples that SIOE will take after detecting the 1-to-0 transition
on SDA of a START condition.
Important note: Keep in mind that the time between samples is always 1/f_OSC.
The minimum START condition hold time, t_HLDSTA, is different for the three common I²C
speed categories per Table 61 on page 126.
Table 59.
Bit 7
EN_SS
S1SETUP: I²C START condition sample setup register (SFR DBh, reset
value 00h)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMPL_SET[6:0]
Bit
Symbol
R/W
Function
Enable Sample Setup
EN_SS = 1 will force the SIOE to sample⁽¹⁾ a START condition
7
EN_SS
R/W on the bus the number of times specified in SMPL_SET[6:0].
EN_SS = 0 means the SIOE will sample⁽¹⁾ a START condition
only one time, regardless of the contents of SMPL_SET[6:0].
SMPL_SET
6:0
[6:0]
Sample Setting
–
Specifies the number of bus samples⁽¹⁾ taken during a START
condition. See Table 60 for values.
Note: 1 Sampling SCL and SDA lines begins after '1'-to-'0' transition on SDA occurred while SCL is
high. Time between samples is 1/f_OSC.
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