UPSD3422_06 Datasheet, PDF (243/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

uPSD34xx
PSD module
register to “output” at run-time for all unused inputs. This will prevent the CMOS input buffers
of unused input pins from drawing excessive current.
The csiop PMMR register definitions are shown in Table 144 through Table 146 on
page 244.
Table 144. Power management mode register PMMR0 (address = csiop + offset B0h)
Bit 0
X
0 Not used, and should be set to zero.
0 Automatic Power Down (APD) counter is disabled.
Bit 1 APD Enable
1 APD counter is enabled
Bit 2
X
0 Not used, and should be set to zero.
Bit 3
PLD Turbo
Disable
0=
on
PLD Turbo mode is on
1=
off
PLD Turbo mode is off, saving power.
Blocking Bit,
Bit 4 CLKIN to
PLDs⁽¹⁾
0 = CLKIN (pin PD1) to the PLD Input Bus is not blocked. Every transition of
on CLKIN powers-up the PLDs.
1 = CLKIN input to PLD Input Bus is blocked, saving power. But CLKIN still
off goes to APD counter.
Bit 5
Blocking Bit,
CLKIN to
OMCs
Only⁽¹⁾
0 = CLKIN input is not blocked from reaching all OMCs’ common clock
on inputs.
1=
off
CLKIN input to common clock of all OMCs is blocked, saving power. But
CLKIN still goes to APD counter and all PLD logic besides the common
clock input on OMCs.
Bit 6
X
0 Not used, and should be set to zero.
Bit 7
X
0 Not used, and should be set to zero.
Note:
All the bits of this register are cleared to zero following Power-up. Subsequent Reset (RST)
pulses do not clear the registers.
Note: 1 Blocking bits should be set to logic ’1’ only if the signal is not needed in a DPLD or GPLD
logic equation.
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