UPSD3422_06 Datasheet, PDF (238/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

PSD module
uPSD34xx
Figure 86. Port B structure
FROM AND-
OR ARRAY
FROM PLD
INPUT BUS
FROM OMC
ALLOCATOR
PT OUTPUT ENABLE (.OE)
PSD MODULE RESET
Q ^DIRECTION
CSIOP
REGIS-
8032
DATA
TERS
Q
DRIVE
BITS _D
8032
WR
Q ^CONTROL
(MCUI/O)
Q ^{DATA OUT}
CLR
RESET
LATCHED ADDR BIT
8032
DATA
BIT
1 ^DIRECTION
P ₂ ^{DRIVE SELECT}
D
B
3
CONTROL
DATA OUT
M ₄ ^(MCUI/O)
U ₅ ^{ENABLE OUT}
X ₆ DATA IN (MCUI/O)
8032 RD
ONE of 6
CSIOP
REGISTERS
FROM OMC OUTPUT
(MCELLABx or MCELLBCx)
I/O PORT B
LOGIC
PSDsoft
OUTPUT
SELECT
1^O
U
T
P
U
2T
3
M
U
X
DRIVE TYPE SELECT⁽¹⁾
1 = OPEN
DRAIN,
PB4 - PB7
1 = FAST
SLEW RATE,
PB0 - PB3
V_DD V_DD
OUTPUT
ENABLE
PIN
OUTPUT
OUTPUT
ENABLE
TYPICAL
PIN, PORT B
CMOS
BUFFER _{PIN INPUT}
NO
HYSTERESIS
TO IMCs
IMCB0 - IMCB7
AI09180
Note: 1 Port pins PB0-PB3 are capable of Fast Slew Rate output drive option. Port pins PB4-PB7
are capable of Open Drain output option.
28.5.49
Port C structure
Port C supports the following operating modes on pins PC2, PC3, PC4, PC7:
● MCU I/O Mode
● GPLD Output Mode from Output Macrocells MCELLBC2, MCELLBC3, MCELLBC4,
MCELLBC7
● GPLD Input Mode to Input Macrocells IMCC2, IMCC3, IMCC4, IMCC7
See Figure 87 on page 239 for detail.
Port C pins can also be configured in PSDsoft for other dedicated functions:
● Pins PC3 and PC4 support TSTAT and TERR status indicators, to reduce the amount
of time required for JTAG ISP programming. These two pins must be used together for
this function, adding to the four standard JTAG signals. When TSTAT and TERR are
used, it is referred to as “6-pin JTAG”. PC3 and PC4 cannot be used for other functions
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