UPSD3422_06 Datasheet, PDF (241/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

uPSD34xx
PSD module
Figure 88. Port D structure
FROM AND-
OR ARRAY
FROM PLD
INPUT BUS
PT OUTPUT ENABLE (.OE)
PSD MODULE RESET
Q ^DIRECTION
CSIOP
REGIS-
8032 ^TERS
DATA
Q
DRIVE
BITS _D
8032
WR
(MCUI/O)
Q ^{DATA OUT}
CLR
RESET
8032
DATA
BIT
P ^{1 DIRECTION}
D ₂ ^{DRIVE SELECT}
B DATA OUT
M
U
3
4
(MCUI/O)
ENABLE OUT
X ₅ DATA IN (MCUI/O)
8032 RD
ONE of 5
CSIOP
REGISTERS
I/O PORT D
LOGIC
PSDsoft
DRIVE TYPE SELECT
1 = FAST
SLEW RATE
1^O
OUTPUT
U
ENABLE
T
P
PIN
U
OUTPUT
2T
OUTPUT
M
ENABLE
U
X
V_DD V_DD
TYPICAL
PIN, PORT D
CMOS
BUFFER _{PIN INPUT}
NO
HYSTERESIS
FROM DPLD
FROM DPLD EXTERNAL CHIP (ECSx)
TO POWER MANAGEMENT AND PLD INPUT BUS
TO POWER MANAGEMENT
DIRECTLY TO PLD INPUT BUS, NO IMC
CLKIN⁽¹⁾
CSI⁽¹⁾
PD1. PIN, PD2.PIN
Note: 1 Optional function on a specific Port D pin.
AI09182
28.5.51
Power management
The PSD Module offers configurable power saving options, and also a way to manage
power to the SRAM (battery backup). These options may be used individually or in
combinations. A top level description for these functions is given here, then more detailed
descriptions will follow.
● Zero-Power Memory: All memory arrays (Flash and SRAM) in the PSD Module are
built with zero-power technology, which puts the memories into standby mode (~ zero
DC current) when 8032 address signals are not changing. As soon as a transition
occurs on any address input, the affected memory “wakes up”, changes and latches its
outputs, then goes back to standby. The designer does not have to do anything special
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