UPSD3422_06 Datasheet, PDF (255/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

uPSD34xx
PSD module
Note:
TSTAT and TERR are functional only when JTAG ISP operations are occurring, which
means they are non-functional during JTAG debugging of the 8032 on the MCU Module.
Programming times vary depending on the number of locations to be programmed and the
JTAG programming equipment, but typical JTAG ISP programming times are 10 to 25
seconds using 6-pin JTAG. The signals TSTAT and TERR are not included in the IEEE
1149.1 specification.
Figure 93 on page 255 shows recommended connections on a circuit board to a JTAG
program/test tool using 6-pin JTAG. It is required to connect the RST output signal from the
JTAG program/test equipment to the RESET_IN input on the uPSD34xx. The RST signal is
driven by the equipment with an Open Drain driver, allowing other sources (like a push
button) to drive RESET_IN without conflict.
The recommended pull-up resistors and decoupling capacitor are illustrated in Figure 93.
Figure 93. Recommended 6-pin JTAG connections
CIRCUIT
BOARD
100k typical
uPSD34xx
TMS - PC0
TCK - PC1
SRAM STBY or I/O - PC2
TSTAT - PC3
TERR - PC4
TDI - PC5
TDO - PC6
GENERAL I/O - PC7
RESETIN
GENERAL I/O
SIGNALS
0.01
µF
10k
JTAG
CONN.
TMS
TCK
TSTAT
TERR
TDI
TDO
V_CC(1,2)
JTAG
Programming
or Test
Equipment
Connects Here
GND
RST⁽³⁾
DEBUG
100k
PUSH BUTTON
or ANY OTHER
RESET SOURCE
OPTIONAL
TEST POINT
AI10458
Note: 1 For 5V uPSD34xx devices, pull-up resistors and V_CC pin on the JTAG connector should be
connected to 5V system V_DD.
2 For 3.3V uPSD34xx devices, pull-up resistors and V_CC pin on the JTAG connector should be
connected to 3.3V system V_CC.
3 This signal is driven by an Open-Drain output in the JTAG equipment, allowing more than
one source to activate RESET_IN.
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