UPSD3422_06 Datasheet, PDF (20/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

Memory organization
uPSD34xx
4.1
4.1.1
4.1.2
4.1.3
Internal memory (MCU module, standard 8032 memory:
DATA, IDATA, SFR)
DATA memory
The first 128 bytes of internal SRAM ranging from address 0x0000 to 0x007F are called
DATA, which can be accessed using 8032 direct or indirect addressing schemes and are
typically used to store variables and stack.
Four register banks, each with 8 registers (R0 – R7), occupy addresses 0x0000 to 0x001F.
Only one of these four banks may be enabled at a time. The next 16 locations at 0x0020 to
0x002F contain 128 directly addressable bit locations that can be used as software flags.
SRAM locations 0x0030 and above may be used for variables and stack.
IDATA memory
The next 128 bytes of internal SRAM are named IDATA and range from address 0x0080 to
0x00FF. IDATA can be accessed only through 8032 indirect addressing and is typically
used to hold the MCU stack as well as data variables. The stack can reside in both DATA
and IDATA memories and reach a size limited only by the available space in the combined
256 bytes of these two memories (since stack accesses are always done using indirect
addressing, the boundary between DATA and IDATA does not exist with regard to the stack).
SFR memory
Special Function Registers (Table 5 on page 32) occupy a separate physical memory, but
they logically overlap the same 128 bytes as IDATA, ranging from address 0x0080 to
0x00FF. SFRs are accessed only using direct addressing. There 86 active registers used
for many functions: changing the operating mode of the 8032 MCU core, controlling 8032
peripherals, controlling I/O, and managing interrupt functions. The remaining unused SFRs
are reserved and should not be accessed.
16 of the SFRs are both byte- and bit-addressable. Bit-addressable SFRs are those whose
address ends in “0” or “8” hex.
4.2
External memory (PSD module: program memory, data
memory)
The PSD Module has four memories: main Flash, secondary Flash, SRAM, and csiop. See
the PSD MODULE section for more detailed information on these memories.
Memory mapping in the PSD Module is implemented with the Decode PLD (DPLD) and
optionally the Page Register. The user specifies decode equations for individual segments
of each of the memories using the software tool PSDsoft Express. This is a very easy point-
and-click process allowing total flexibility in mapping memories. Additionally, each of the
memories may be placed in various combinations of 8032 program address space or 8032
data address space by using the software tool PSDsoft Express.
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