UPSD3422_06 Datasheet, PDF (43/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

uPSD34xx
uPSD34xx instruction set summary
Mnemonic⁽¹⁾ and Use
INC
MUL
DIV
DA
DPTR
AB
AB
A
Description
Increment Data Pointer
Multiply ACC and B
Divide ACC by B
Decimal adjust ACC
Note: 1 All mnemonics copyrighted ©Intel Corporation 1980.
Table 7. Logical instruction set
Mnemonic⁽¹⁾ and Use
Description
Logical Instructions
ANL
A, Rn
AND register to ACC
ANL
A, direct
AND direct byte to ACC
ANL
A, @Ri
AND indirect SRAM to ACC
ANL
ANL
ANL
ORL
A, #data
direct, A
direct, #data
A, Rn
AND immediate data to ACC
AND ACC to direct byte
AND immediate data to direct byte
OR register to ACC
ORL
ORL
ORL
ORL
ORL
A, direct
A, @Ri
A, #data
direct, A
direct, #data
OR direct byte to ACC
OR indirect SRAM to ACC
OR immediate data to ACC
OR ACC to direct byte
OR immediate data to direct byte
SWAP
XRL
XRL
XRL
A
A, Rn
A, direct
A, @Ri
Swap nibbles within the ACC
Exclusive-OR register to ACC
Exclusive-OR direct byte to ACC
Exclusive-OR indirect SRAM to ACC
XRL
A, #data
Exclusive-OR immediate data to ACC
XRL
direct, A
Exclusive-OR ACC to direct byte
XRL
direct, #data Exclusive-OR immediate data to direct byte
CLR
A
Clear ACC
CPL
A
Compliment ACC
RL
A
RLC
A
RR
A
RRC
A
Rotate ACC left
Rotate ACC left through the carry
Rotate ACC right
Rotate ACC right through the carry
Note: 1 All mnemonics copyrighted ©Intel Corporation 1980.
Length/Cycles
1 byte/2 cycle
1 byte/4 cycle
1 byte/4 cycle
1 byte/1 cycle
Length/Cycles
1 byte/1 cycle
2 byte/1 cycle
1 byte/1 cycle
2 byte/1 cycle
2 byte/1 cycle
3 byte/2 cycle
1 byte/1 cycle
2 byte/1 cycle
1 byte/1 cycle
2 byte/1 cycle
2 byte/1 cycle
3 byte/2 cycle
1 byte/1 cycle
1 byte/1 cycle
2 byte/1 cycle
1 byte/1 cycle
2 byte/1 cycle
2 byte/1 cycle
3 byte/2 cycle
1 byte/1 cycle
1 byte/1 cycle
1 byte/1 cycle
1 byte/1 cycle
1 byte/1 cycle
1 byte/1 cycle
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