UPSD3422_06 Datasheet, PDF (137/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

uPSD34xx
SPI (synchronous peripheral interface)
Figure 47. SPI transmit operation example
SPICLK
(SPO=0)
1 frame
SPICLK
(SPO=1)
SPITXD
Bit0
Bit1
Bit7
Bit0
Bit1
Bit7
TISF
TEISF
BUSY
SPISEL
SPIINTR
SPITDR Empty
interrupt requested
Interrupt handler
write data in TDR
SPITDR Empty
interrupt requested
Transmit End
interrupt requested
AI07854
24.4
SPI SFR registers
Six SFR registers control the SPI interface:
● SPICON0 (Table 63) for interface control
● SPICON1 (Table 64) for interrupt control
● SPITDR (SFR D4h, Write only) holds byte to transmit
● SPIRDR (SFR D5h, Read only) holds byte received
● SPICLKD (Table 65) for clock divider
● SPISTAT (Table 66 on page 142) holds interface status
The SPI interface functional block diagram (Figure 48) shows these six SFRs. Both the
transmit and receive data paths are double-buffered, meaning that continuous transmitting
or receiving (back-to-back transfer) is possible by reading from SPIRDR or writing data to
SPITDR while shifting is taking place. There are a number of flags in the SPISTAT register
that indicate when it is full or empty to assist the 8032 MCU in data flow management. When
enabled, these status flags will cause an interrupt to the MCU.
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