UPSD3422_06 Datasheet, PDF (154/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

USB interface
uPSD34xx
Note:
25.4.1
25.4.2
SFR
Addr
SFR
(hex) ^{Name 7 6}
EB
UIF3
–
–
EC UCTL –
–
ED
USTA –
–
EE
EF
USEL DIR –
F1 UCON –
–
F2 USIZE –
F3 UBASEH
F4
UBASEL
BASEADDR
[7:6]
F5
USCI –
–
F6
USCV
Bit Name and <Bit Address>
5
4
3
2
1
Reset
Value Comment
0 (hex)
–
NAK4F NAK3F NAK2F NAK1F NAK0F
00
USB IN FIFO
NAK Int. Flag
–
–
–
USBEN VISIBLE WAKEUP 00
USB Control
–
–
RCVT SETUP
IN
OUT
00
USB Status
RESERVED
–
–
–
EP[2:0]
00
USB Endpoint
Select
–
–
ENABLE STALL
TOGGL
E
BSY
08
USB Endpoint
Control
SIZE[6:0]
00
USB FIFO
Valid Size
BASEADDR[15:8]
00
USB Base
Address High
0
0
0
0
0
0
00
USB Base
Address Low
–
–
–
USCI[2:0]
USB Setup
00
Command
Index
USCV[7:0]
USB Setup
00
Command
Value
Bits marked with a “–“ are Reserved.
USB device address register
Initially when a device is connected to the USB, it responds to the host on address 0. Using
the Set_Address request, the host assigns a unique address to the device. The firmware
writes this address to the USB Device Address register (see Table 70), and subsequently
the SIE only responds to transactions on that assigned address. This assigned address is in
effect until the device or an upstream hub is disconnected from the USB, the host issues a
USB Reset, or the host shuts down. The address register is cleared with a Hardware
RESET. When a USB RESET is detected, the address register should be cleared.
Endpoint FIFO pairing
Endpoint FIFOs can be paired for double buffering to provide an efficient method for bulk
data transfers. With double buffering enabled, the MCU can operate on one data packet
while another is being transferred over USB.
When two FIFOs are paired, the active FIFO is automatically toggled by the update of
USIZE. The MCU must only use the odd numbered endpoint FIFO when paired in order to
access the active FIFO. For example, if endpoints 3 and 4 OUT FIFOs are paired, the active
FIFO is accessed via endpoint 3’s OUT FIFO (see Table 71).
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