UPSD3422_06 Datasheet, PDF (235/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

uPSD34xx
PSD module
mode, making the pin suitable for input mode (read by the input buffer shown in Figure 80 on
page 226). Figure 80 shows the three sources that can control the pin output enable signal:
a product term from AND-OR array; the csiop Direction register; or the Peripheral I/O Mode
logic (Port A only). The csiop Enable Out registers represent the state of the final output
enable signal for each port pin driver, and are defined in Table 140 on page 236 through
Table 143 on page 236.
Table 136. Port A pin drive select register⁽¹⁾ (address = csiop + offset 08h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PA7
Open Drain
PA6
Open Drain
PA5
Open Drain
PA4
Open Drain
PA3
Slew Rate
PA2
Slew Rate
PA1
Slew Rate
PA0
Slew Rate
Note: 1 Port A not available on 52-pin uPSD34xx devices
2 For each bit, 1 = pin drive type is selected, 0 = pin drive type is default mode, CMOS
push/pull
3 Default state for register is 00h after reset or power-up
Table 137. Port B pin drive select register (address = csiop + offset 09h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PB7
Open Drain
PB6
Open Drain
PB5
Open Drain
PB4
Open Drain
PB3
Slew Rate
PB2
Slew Rate
PB1
Slew Rate
Bit 0
PB0
Slew Rate
Note: 1 For each bit, 1 = pin drive type is selected, 0 = pin drive type is default mode, CMOS
push/pull
2 Default state for register is 00h after reset or power-up
Table 138. Port C pin drive select register (address = csiop + offset 16h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PC7
Open Drain
N/A (JTAG)
N/A (JTAG)
PC4
Open Drain
PC3
Open Drain
PC2
Open Drain
N/A (JTAG)
Bit 0
N/A (JTAG)
Note: 1 For each bit, 1 = pin drive type is selected, 0 = pin drive type is default mode, CMOS
push/pull
2 Default state for register is 00h after reset or power-up
Table 139. Port D pin drive select register (address = csiop + offset 17h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
N/A
N/A
N/A
N/A
N/A
PD2⁽³⁾
Slew Rate
PD1
Slew Rate
Bit 0
N/A
Note: 1 For each bit, 1 = pin drive type is selected, 0 = pin drive type is default mode, CMOS
push/pull
2 Default state for register is 00h after reset or power-up
3 Pin is not available on 52-pin uPSD34xx devices
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