UPSD3422_06 Datasheet, PDF (251/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

uPSD34xx
PSD module
In PLD I/O mode, pins of Ports A, B, C, and D may also float during reset if no external
device is driving them, and if there is no equation specified for the DPLD or GPLD to make
them an output. In this case, a weak external pull-up resistor (100KΩ minimum) should be
used on floating pins to avoid excessive current draw.
The pins on Ports 1, 3, and 4 of the 8032 MCU module do have weak internal pull-ups and
the inputs will not float, so no external pull-ups are needed.
Table 148. Function status during power-up reset, warm reset, power-down mode
Port Configuration
Power-Up Reset
Warm Reset
APD Power-down
Mode
MCU I/O
Pins are in input mode Pins are in input mode
Pin logic state is
unchanged
PLD I/O
Pin logic is valid after
internal PSD Module
configuration bits are
loaded. Happens long
before RST is de-
asserted
Pin logic is valid and is
determined by PLD
logic equations
Pin logic depends on
inputs to PLD (8032
addresses are blocked
from reaching PLD
inputs during power-
down mode)
Latched Address Out
Mode
Pins are High
Impedance
Pins are High
Impedance
Pins logic state not
defined since 8032
address signals are
blocked
Peripheral I/O Mode
Pins are High
Impedance
Pins are High
Impedance
Pins are High
Impedance
JTAG ISP and Debug
JTAG channel is active JTAG channel is active JTAG channel is active
and available
and available
and available
Register
PMMR0 and PMMR2
Output of OMC Flip-
flops
VM Register⁽¹⁾
All other csiop registers
Power-Up Reset
Cleared to 00h
Cleared to ’0’
Initialized with value
that was specified in
PSDsoft
Cleared to 00h
Warm Reset
APD Power-down
Mode
Unchanged
Unchanged
Depends on .re and .pr Depends on .re and .pr
equations
equations
Initialized with value
that was specified in
PSDsoft
Unchanged
Cleared to 00h
Unchanged
Note: 1 VM register Bit 7 (PIO_EN) and Bit 0 (SRAM in 8032 program space) are cleared to zero at
power-up and warm reset conditions.
28.6.1
JTAG ISP and JTAG debug
An IEEE 1149.1 serial JTAG interface is used on uPSD34xx devices for ISP (In-System
Programming) of the PSD module, and also for debugging firmware on the MCU Module.
IEEE 1149.1 Boundary Scan operations are not supported in the uPSD34xx.
The main advantage of JTAG ISP is that a blank uPSD34xx device may be soldered to a
circuit board and programmed with no involvement of the 8032, meaning that no 8032
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