UPSD3422_06 Datasheet, PDF (155/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

uPSD34xx
USB interface
Table 70. USB device address register (UADDR 0E2h, reset value 00h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
–
USBADDR[6:0]
Bit 0
Bit Symbol
R/W
Definition
7
–
–
Reserved
USB Address of the device.
6:0 USBADDR R/W These bits are cleared with a Hardware RESET. When a USB
RESET is detected, the address register should be cleared.
Table 71.
Bit 7
–
Pairing control register (UPAIR 0E3h, reset value 00h)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
–
–
–
PR3OUT PR1OUT PR3IN
Bit 0
PR1IN
25.4.3
Bit
Symbol
R/W
Definition
7
–
–
Reserved
6
–
–
Reserved
5
–
–
Reserved
4
–
–
Reserved
Setting this bit enables double buffering of the OUT FIFOs for
3
PR3OUT
R/W Endpoints 3 and 4. Access to the double buffered FIFOs is
through Endpoint3’s OUT FIFO.
Setting this bit enables double buffering of the OUT FIFOs for
2
PR1OUT
R/W Endpoints 1 and 2. Access to the double buffered FIFOs is
through Endpoint1’s OUT FIFO.
Setting this bit enables double buffering of the IN FIFOs for
1
PR3IN
R/W Endpoints 3 and 4. Access to the double buffered FIFOs is
through Endpoint3’s IN FIFO.
Setting this bit enables double buffering of the IN FIFOs for
0
PR1IN
R/W Endpoints 1 and 2. Access to the double buffered FIFOs is
through Endpoint1’s IN FIFO.
USB interrupts
There are many USB related events that generate an interrupt. The events that generate an
interrupt are selectively enabled through the use of the USB Interrupt Enable Registers. All
USB interrupts are serviced through a single interrupt vector (see Section 13: Interrupt
system on page 52 for the address of the interrupt vector). When a USB interrupt occurs,
firmware must check the USB Interrupt Flag Registers to determine the source of the
interrupt, clear that interrupt flag and process the interrupt before returning to the interrupted
code.
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