UPSD3422_06 Datasheet, PDF (150/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

USB interface
uPSD34xx
25.3.3
Note:
Table 68.
Endpoint
uPSD34xx supported endpoints
Function
Max packet size
(FIFO size)
0
Control
64 Bytes
0
Control
64 Bytes
1
Bulk/Interrupt OUT
1
Bulk/Interrupt IN
64 Bytes
64 Bytes
2
Bulk/Interrupt OUT
64 Bytes
2
Bulk/Interrupt IN
64 Bytes
3
Bulk/Interrupt OUT
3
Bulk/Interrupt IN
64 Bytes
64 Bytes
4
Bulk/Interrupt OUT
64 Bytes
4
Bulk/Interrupt In
64 Bytes
Supported directions
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
FIFO pairing
The FIFOs on endpoints 1 through 4 may be used independently as shown in Figure 54 as
FIFOs with no Pairing or they may be selectively paired to provide double buffering (see
Figure 55 on page 152). Double buffering provides an efficient way to optimize data transfer
rates with bulk transfers. Double buffering allows the CPU to process a data packet for an
Endpoint while the SIE is receiving or transmitting another packet of data on the same
Endpoint and direction. FIFO pairing is controlled by the USB Pairing Control Register (see
UPAIR, Table 71 on page 155). FIFO pairing options are listed below:
● IN FIFO 1 and 2
● OUT FIFO 1 and 2
● IN FIFO 3 and 4
● OUT FIFO 3 and 4
When the FIFOs are paired, the CPU must access the odd numbered FIFO while the even
numbered FIFOs are no longer available for use. Also when they are paired, the active FIFO
is automatically toggled by the update of USIZE.
● Non-pairing FIFOs Example
Consider a case where the device needs to send 1024 bytes of data to the host.
Without FIFO pairing (see Figure 54), the CPU loads the IN Endpoint0 FIFO with 64
bytes of data and waits until the host sends an IN token to Endpoint0, and the SIE
transfers the data to the host. Once all 64 bytes have been transferred by the SIE, the
FIFO becomes empty and the CPU starts writing the next 64 bytes of data to the FIFO.
While the CPU is writing the data to the FIFO, the host is sending IN tokens to
Endpoint0, requesting the next 64 bytes of data, but only gets NAKs while the FIFO is
being loaded. Once the FIFO has been loaded by the CPU, the SIE starts sending the
data to the host with the next IN Endpoint0 token. Again, the CPU waits until the SIE
transfers the 64 bytes of data to the host. This is repeated until all 1024 bytes have
been transferred.
150/293