UPSD3422_06 Datasheet, PDF (86/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

Supervisory functions
uPSD34xx
19.5.1
In this example,
t_{MACH_CYC} = 100ns (4 MCU_CLK periods x 25ns)
N_OVERFLOW = 2²⁴ = 16777216 up-counts
WDT_PERIOD = 100ns X 16777216 = 1.67 seconds
The actual value will be slightly longer due to PFQ/BC.
Firmware Example:
The following 8051 assembly code illustrates how to operate the WDT. A simple statement
in the reset initialization firmware enables the WDT, and then a periodic write to clear the
WDT in the main firmware is required to keep the WDT from overflowing. This firmware is
based on the example above (40MHz f_OSC, CCON0 = 10h, BUSCON = C1h).
For example, in the reset initialization firmware (the function that executes after a jump to
the reset vector):
MOV AE, #AA
; enable WDT by writing value to
; WDKEY other than 55h
Somewhere in the flow of the main program, this statement will execute periodically to reset
the WDT before its time-out period of 1.67 seconds. For example:
MOV A6, #00
; reset WDT, loading 000000h.
; Counting will automatically
; resume as long as 55h in not in
; WDKEY
Table 39.
Bit 7
WDKEY: Watchdog timer key register (SFR AEh, reset value 55h)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WDKEY[7:0]
Bit
Symbol
R/W
Definition
[7:0]
WDKEY
55h disables the WDT from counting. 55h is automatically
loaded in this SFR after any reset condition, leaving the WDT
W
disabled by default.
Any value other than 55h written to this SFR will enable the
WDT, and counting begins.
Table 40.
Bit 7
WDRST: Watchdog timer reset counter register (SFR A6h, reset value
00h)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WDRST[7:0]
Bit
Symbol
R/W
Definition
[7:0]
WDRST
This SFR is the upper byte of the 24-bit WDT up-counter.
Writing this SFR sets the upper byte of the counter to the
W
written value, and clears the lower two bytes of the counter to
0000h.
Counting begins when WDKEY does not contain 55h.
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