UPSD3422_06 Datasheet, PDF (227/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

uPSD34xx
PSD module
Port Operating Mode
Port A (80-pin
only)
Port B
Latched Address Output
Yes
Yes
Peripheral I/O Mode
JTAG ISP
Yes
No
No
No
Port C Port D
Find it
No
No
Yes⁽²⁾
Latched address
No
output mode on
page 232
No
Peripheral I/O mode
on page 233
No
JTAG ISP mode on
page 234
Note: 1 MCELLBC outputs available only on pins PC2, PC3, PC4, and PC7.
2 JTAG pins (PC0/TMS, PC1/TCK, PC5/TDI, PC6/TDO) are dedicated to JTAG pin functions
(cannot be used for general I/O).
Table 121. Port Configuration Setting Requirements
Port
Operating
Mode
Required Action in
PSDsoft Express to
Configure each Pin
Value that 8032
writes to csiop
Control Register
at run-time
Value that 8032
writes to csiop
Direction
Register at run-
time
Value that 8032
writes to Bit 7
(PIO_EN) of csiop
VM Register at
run-time
MCU I/O
Logic 1 = Out of
Choose the MCU I/O
uPSD
function and declare Logic '0' (default)
N/A
the pin name
Logic 0 = Into
uPSD
PLD I/O
Choose the PLD
function type, declare
pin name, and specify
N/A
logic equation(s)
Direction register
has no effect on a
pin if pin is driven
N/A
from OMC output
Latched
Address Output
Choose Latched
Address Out function,
declare pin name
Logic '1'
Logic '1' Only
N/A
Choose Peripheral
I/O mode function
PIO_EN Bit = Logic
Peripheral I/O and specify address N/A
N/A
1
range in DPLD for
(default is '0')
PSELx
No action required in
PSDsoft to get 4-pin
4-PIN JTAG ISP
JTAG. By default
TDO, TDI, TCK, TMS
N/A
N/A
N/A
are dedicated JTAG
functions.
6-PIN JTAG ISP ^{Choose JTAG TSTAT}
(faster
function for pin PC3
and JTAG TERR
N/A
N/A
N/A
programming) _{function for pin PC4.}
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