UPSD3422_06 Datasheet, PDF (15/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

uPSD34xx
Pin descriptions
Table 2. Pin definitions
Port Pin
Signal
Name
80-Pin
No.
52-Pin
No.⁽¹⁾
In/Out
Basic
PSEN
ALE
RESET_IN
XTAL1
XTAL2
DEBUG
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
JTAGTMS
JTAGTCK
TMS
TCK
63 N/A
O
PSEN Signal,
external bus
4
N/A
O
Address Latch
signal, external bus
68 44
I
Active low reset
input
48 31
I
Oscillator input pin
for system clock
49 32
O
Oscillator output pin
for system clock
8
5
I/O
I/O to the MCU
Debug Unit
35 N/A I/O General I/O port pin
34 N/A I/O General I/O port pin
32 N/A I/O General I/O port pin
28 N/A I/O General I/O port pin
26 N/A I/O General I/O port pin
24 N/A I/O General I/O port pin
22 N/A I/O General I/O port pin
21 N/A I/O General I/O port pin
80 52 I/O General I/O port pin
78 51 I/O General I/O port pin
76 50 I/O General I/O port pin
74 49 I/O General I/O port pin
73 48 I/O General I/O port pin
71 46 I/O General I/O port pin
67 43 I/O General I/O port pin
66 42 I/O General I/O port pin
20 13
I JTAG pin (TMS)
17 12
I JTAG pin (TCK)
PC2
V_STBY
16
11
I/O General I/O port pin
PC3
TSTAT 15 N/A I/O General I/O port pin
PC4
TERR
9
N/A I/O General I/O port pin
Function
Alternate 1
Alternate 2
All Port A pins
support:
1. PLD Macro-
cell outputs, or
2. PLD inputs, or
3. Latched
Address Out
(A0-A7), or
4. Peripheral I/O
Mode
All Port B pins
support:
1. PLD Macro-
cell outputs, or
2. PLD inputs, or
3. Latched
Address Out
(A0-A7 or
A8-A15)
SRAM Standby
voltage input
(V_STBY)
Optional JTAG
Status (TSTAT)
Optional JTAG
Status (TERR)
PLD Macrocell
output, or PLD input
PLD, Macrocell
output, or PLD input
PLD, Macrocell
output, or PLD input
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