UPSD3422_06 Datasheet, PDF (64/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

Power saving modes
uPSD34xx
15.2
Power-down Mode
Power-down Mode will halt the 8032 core and all MCU peripherals (Power-down Mode
blocks MCU_CLK, USB_CLK, and PERIPH_CLK). This is the lowest power state for the
MCU Module. When the PSD Module is also placed in Power-down mode, the lowest total
current consumption for the combined die is achieved for the uPSD34xx. See
Section 28.1.16: Power management on page 191 in the PSD Module section for details on
how to also place the PSD Module in Power-down mode. The sequence of 8032 instructions
is important when placing both modules into Power-down Mode.
The instruction that sets the PD Bit in the SFR named PCON (Table 26 on page 66) is the
last instruction executed prior to the MCU Module going into Power-down Mode. Once in
Power-down Mode, the on-chip oscillator circuitry and all clocks are stopped. The SFRs,
DATA, IDATA, and XDATA are preserved.
Power-down Mode is terminated only by a reset from the supervisor, originating from the
RESET_IN_ pin, the Low-Voltage Detect circuit (LVD), or a JTAG Debug reset command.
Since the clock to the WTD is not active during Power-down mode, it is not possible for the
supervisor to generate a WDT reset.
Table 24 on page 65 summarizes the status of I/O pins and peripherals during Idle and
Power-down Modes on the MCU Module. Table 25 on page 65 shows the state of 8032
MCU address, data, and control signals during these modes.
15.3
Note:
Reduced Frequency Mode
The 8032 MCU consumes less current when operating at a lower clock frequency. The MCU
can reduce its own clock frequency at run-time by writing to three bits, CPUPS[2:0], in the
SFR named CCON0 described in Table 22 on page 62. These bits effectively divide the
clock frequency (f_OSC) coming in from the external crystal or oscillator device. The clock
division range is from 1/2 to 1/2048, and the resulting frequency is f_MCU.
This MCU clock division does not affect any of the peripherals, except for the WTD. The
clock driving the WTD is the same clock driving the 8032 MCU core as shown in Figure 14
on page 61.
MCU firmware may reduce the MCU clock frequency at run-time to consume less current
when performing tasks that are not time critical, and then restore full clock frequency as
required to perform urgent tasks.
Returning to full clock frequency is done automatically upon an MCU interrupt, if the CPUAR
Bit in the SFR named CCON0 is set (the interrupt will force CPUPS[2:0] = 000). This is an
excellent way to conserve power using a low frequency clock until an event occurs that
requires full performance. See Table 22 on page 62 for details on CPUAR.
See the DC Specifications at the end of this document to estimate current consumption
based on the MCU clock frequency.
Some of the bits in the PCON SFR shown in Table 26 on page 66 are not related to power
control.
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