UPSD3422_06 Datasheet, PDF (224/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

PSD module
uPSD34xx
If the user would like to latch an incoming signal using the gate signal ALE from the 8032,
then in PSDsoft Express, for a given input pin on Port A, B, or C, specify “Latched Address”
as the pin function.
If it is desired to pass an incoming signal through an IMC directly to the AND-OR array
inputs without clocking or gating (this is most common), in PSDsoft Express simply specify
“Logic or Address” for the input pin function on Port A, B, or C.
Figure 79. Detail of a single IMC
TO PLD INPUT BUS
FROM AND-OR ARRAY
8032 READ OF PARTICULAR CSIOP IMC REGISTER
8032 DATA BIT
ALE
PIN INPUT
M
U ^{LATCHED INPUT} _{Q D}
X _{GATED INPUT}
(.LD)
PSDsoft
PSDsoft
ALE
M
U
PT CLOCK OR GATE (.LD OR .LE) X
QD
(.LE)
G
FROM I/O PORT
LOGIC
INPUT SIGNAL
FROM PIN ON
PORT A, B, or C
INPUT MACROCELL (IMC)
THIS SIGAL IS GANGED TO 3 OTHER
IMCs, GROUPING IMC 0 - 3 or IMC 4 - 7.
AI06603A
Table 117. Input macrocell Port A⁽¹⁾ (address = csiop + offset 0Ah)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
IMC PA7 IMC PA6 IMC PA5 IMC PA4 IMC PA3 IMC PA2 IMC PA1
Bit 0
IMC PA0
Note: 1 Port A not available on 52-pin uPSD34xx devices
2 1 = current state of IMC is logic '1,' 0 = current state is logic ’0’
Table 118. Input macrocell Port B (address = csiop + offset 0Bh)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
IMC PB7 IMC PB6 IMC PB5 IMC PB4 IMC PB3 IMC PB2 IMC PB1
Bit 0
IMC PB0
Note:
1 = current state of IMC is logic '1,' 0 = current state is logic ’0’
Table 119. Input macrocell Port C (address = csiop + offset 18h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
IMC PC7
X
X
IMC PC4 IMC PC3 IMC PC2
X
Bit 0
X
Note: 1 X = Not guaranteed value, can be read either '1' or '0.' These are JTAG pins.
2 1 = current state of IMC is logic '1,' 0 = current state is logic ’0’
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