UPSD3422_06 Datasheet, PDF (223/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

uPSD34xx
PSD module
28.5.32
OMC mask registers
There is one OMC Mask Register for each of the two groups of eight OMCs shown in
Table 115 and Table 116. The OMC mask registers are used to block loading of data to
individual OMCs. The default value for the mask registers is 00h, which allows loading of all
OMCs. When a given bit in a mask register is set to a '1,' the 8032 is blocked from writing to
the associated OMC flip-flop. For example, suppose that only four of eight OMCs
(MCELLAB0-3) are being used for a state machine. The user may not want the 8032 to write
to all the OMCs in MCELLAB because it would overwrite the state machine registers.
Therefore, the user would want to load the mask register for MCELLAB with the value 0Fh
before writing OMCs.
Table 115. Output macrocell MCELLAB mask register (address = csiop + offset 22h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mask
MCELLAB7
Mask
MCELLAB6
Mask
MCELLAB5
Mask
MCELLAB4
Mask
MCELLAB3
Mask
MCELLAB2
Mask
MCELLAB1
Mask
MCELLAB0
Note: 1 Default is 00h after any reset condition
2 1 = block writing to individual macrocell, 0 = allow writing to individual macrocell
Table 116. Output macrocell MCELLBC mask register (address = csiop + offset 23h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mask
Mask
Mask
Mask
Mask
Mask
Mask
Mask
MCELLBC7 MCELLBC6 MCELLBC5 MCELLBC4 MCELLBC3 MCELLBC2 MCELLBC1 MCELLBC0
Note: 1 Default is 00h after any reset condition
2 1 = block writing to individual macrocell, 0 = allow writing to individual macrocell
28.5.33
Input macrocells
The GPLD has 20 IMCs, one for each pin on Port A (80-pin device only), one for each pin on
Port B, and for the four pins on Port C that are not JTAG pins. The architecture of one
individual IMC is shown in Figure 79 on page 224. IMCs are individually configurable, and
they can strobe a signal coming in from a port pin as a latch (gated), or as a register
(clocked), or the IMC can pass the signal without strobing, all prior to driving the signal onto
the PLD input bus. Strobing is useful for sampling and debouncing inputs (keypad inputs,
etc.) before entering the PLD AND-OR arrays. The outputs of IMCs can be read by the 8032
asynchronously when the 8032 reads the csiop registers shown in Table 117, Table 118,
and Table 119 on page 224. It is possible to read a PSD Module port pin using one of two
different methods, one method is by reading IMCs as described here, the other method is
using MCU I/O mode described in a later section.
The optional IMC clocking or gating signal used to strobe pin inputs is driven by a product
term from the AND-OR array. There is one clocking or gating product term available for each
group of four IMCs. Port inputs 0-3 are controlled by one product term and 4-7 by another.
To specify in PSDsoft Express the method in which a signal will be strobed as it enters an
IMC for a given input pin on Port A, B, or C, just specify “PT Clocked Register” to use a rising
edge to clock the incoming signal, or specify “PT Clock Latch” to use an active high gate
signal to latch the incoming signal. Then define an equation for the IMC clock (.ld) or the
IMC gate (.le) signal in the “I/O Equations” section.
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