UPSD3422_06 Datasheet, PDF (183/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

uPSD34xx
Programmable counter array (PCA) with PWM
Table 98.
Bit 7
OVF1
PCA status register PCASTA (SFR 0A5h, reset value 00h)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
INTF5
INTF4
INTF3
OVF0
INTF2
INTF1
Bit 0
INTF0
Bit
Symbol
Function
PCA1 Counter OverFlow flag
7
OFV1 ^{Set by hardware when the counter rolls over. OVF1 flags an interrupt if Bit}
EOVFI in PCACON1 is set. OVF1 may be set with either hardware or
software but can only be cleared with software.
TCM5 Interrupt flag
6
INTF5 Set by hardware when a match or capture event occurs.
Must be clear with software.
TCM4 Interrupt flag
5
INTF4 Set by hardware when a match or capture event occurs.
Must be clear with software.
TCM3 Interrupt flag
4
INTF3 Set by hardware when a match or capture event occurs.
Must be clear with software.
PCA0 Counter OverFlow flag
3
OVF0 ^{Set by hardware when the counter rolls over. OVF0 flags an interrupt if Bit}
EOVFI in PCACON0 is set. OVF1 may be set with either hardware or
software but can only be cleared with software.
TCM2 Interrupt flag
2
INTF2 Set by hardware when a match or capture event occurs.
Must be clear with software.
TCM1 Interrupt flag
1
INTF1 Set by hardware when a match or capture event occurs.
Must be clear with software.
TCM0 Interrupt flag
0
INTF0 Set by hardware when a match or capture event occurs.
Must be clear with software.
27.13
TCM interrupts
There are 8 TCM interrupts: 6 match or capture interrupts and two counter overflow
interrupts. The 8 interrupts are “ORed” as one PCA interrupt to the CPU.
By the nature of PCA application, it is unlikely that many of the interrupts occur
simultaneously. If they do, the CPU has to read the interrupt flags and determine which one
to serve. The software has to clear the interrupt flag in the Status Register after serving the
interrupt.
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