UPSD3422_06 Datasheet, PDF (192/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

PSD module
uPSD34xx
28.2.1
28.2.2
8032 program address space
In the example of Figure 64, six sectors of Main Flash memory (fs2.. fs7) are paged across
three memory pages in the upper half of program address space, and the remaining two
sectors of Main Flash memory (fs0, fs1) reside in the lower half of program address space,
and these two sectors are independent of paging (they reside in “common” program address
space). This paged memory example is quite common and supported by many 8051
software compilers.
8032 data address space (XDATA)
Four sectors of Secondary Flash memory reside in the upper half of 8032 XDATA space in
the example of Figure 64. SRAM and csiop registers are in the lower half of XDATA space.
The 8032 SFR registers and local SRAM inside the 8032 MCU Module do not reside in
XDATA space, so it is OK to place PSD Module SRAM or csiop registers at an address that
overlaps the address of internal 8032 MCU Module SRAM and registers.
Figure 64. Typical system memory map
8032 PROGRAM SPACE
(PSEN)
Page 0 Page 1 Page 2
FFFFh
fs3
16KB
C000h
fs5
16KB
fs7
16KB
8000h
fs2
16KB
fs4
16KB
fs6
16KB
8032 XDATA
SPACE
(RD and WR)
Page X
csboot3
8KB
FFFFh
E000h
csboot2
8KB _C000h
csboot1
8KB
csboot0
8KB
A000h
8000h
fs1, 16KB
Common Memory to All Pages
4000h
fs0, 16KB
Common Memory to All Pages
0000h
System
I/O
csiop
256B 2000h
rs0, 8KB
0000h
AI09173
28.2.3
Specifying the memory map with PSDsoft express
The memory map example shown in Figure 64 on page 192 is implemented using PSDsoft
Express in a point-and-click environment. PSDsoft Express will automatically generate
Hardware Definition Language (HDL) statements of the ABEL language for the DPLD, such
as those shown in Table 103.
Specifying these equations using PSDsoft Express is very simple. For example, Figure 65,
page 84 shows how to specify the chip-select equation for the 16K byte Flash memory
segment, fs4. Notice fs4 is on memory page 1. This specification process is repeated for all
other Flash memory segments, the SRAM, the csiop register block, and any external chip
select signals that may be needed.
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