UPSD3422_06 Datasheet, PDF (171/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

uPSD34xx
Analog-to-digital convertor (ADC)
26 Analog-to-digital convertor (ADC)
The ADC unit in the uPSD34xx is a SAR type ADC with an SAR register, an auto-zero
comparator and three internal DACs. The unit has 8 input channels with 10-bit resolution.
The A/D converter has its own AV_REF input (80-pin package only), which specifies the
voltage reference for the A/D operations. The analog to digital converter (A/D) allows
conversion of an analog input to a corresponding 10-bit digital value. The A/D module has
eight analog inputs (P1.0 through P1.7) to an 8x1 multiplexor. One ADC channel is selected
by the bits in the configuration register. The converter generates a 10-bits result via
successive approximation. The analog supply voltage is connected to the AV_REF input,
which powers the resistance ladder in the A/D module.
The A/D module has 3 registers, the control register ACON, the A/D result register ADAT0,
and the second A/D result register ADAT1. The ADAT0 Register stores Bits 0.. 7 of the
converter output, Bits 8.. 9 are stored in Bits 0..1 of the ADAT1 Register. The ACON
Register controls the operation of the A/D converter module. Three of the bits in the ACON
Register select the analog channel inputs, and the remaining bits control the converter
operation.
ADC channel pin input is enabled by setting the corresponding bit in the P1SFS0 and
P1SFS1 Registers to '1' and the channel select bits in the ACON Register.
The ADC reference clock (ADCCLK) is generated from f_OSC divided by the divider in the
ADCPS Register. The ADC operates within a range of 2 to 16MHz, with typical ADCCLK
frequency at 8MHz.
The conversion time is 4µs typical at 8MHz.
The processing of conversion starts when the Start Bit ADST is set to '1.' After one cycle, it
is cleared by hardware. The ADC is monotonic with no missing codes. Measurement is by
continuous conversion of the analog input. The ADAT Register contains the results of the
A/D conversion. When conversion is complete, the result is loaded into the ADAT. The A/D
Conversion Status Bit ADSF is set to '1.' The block diagram of the A/D module is shown in
Figure 57. The A/D status bit ADSF is set automatically when A/D conversion is completed
and cleared when A/D conversion is in process.
In addition, the ADC unit sets the interrupt flag in the ACON Register after a conversion is
complete (if AINTEN is set to '1'). The ADC interrupts the CPU when the enable bit AINTEN
is set.
26.1
Note:
Port 1 ADC channel selects
The P1SFS0 and P1SFS1 Registers control the selection of the Port 1 pin functions. When
the P1SFS0 Bit is '0,' the pin functions as a GPIO. When bits are set to '1,' the pins are
configured as alternate functions. A new P1SFS1 Register selects which of the alternate
functions is enabled. The ADC channel is enabled when the bit in P1SFS1 is set to '1.'
In the 52-pin package, there is no individual AV_REF pin because AV_REF is combined with
AV_CC pin.
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