UPSD3422_06 Datasheet, PDF (188/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

PSD module
uPSD34xx
28.1.8
signals used to “page” memory beyond the 64K byte limit (program space or XDATA). Most
8051 compilers directly support memory paging, also known as memory banking. If memory
paging is not needed, or if not all eight page register bits are needed for memory paging, the
remaining bits may be used in the General PLD for general logic. Page Register outputs are
cleared to logic ’0’ at reset and power-up.
Programmable logic (PLDs)
The uPSD34xx contains two PLDs (Figure 74 on page 215) that may optionally run in Turbo
or Non-Turbo mode. PLDs operate faster (less propagation delay) while in Turbo mode but
consume more power than in Non-Turbo mode. Non-Turbo mode allows the PLDs to go to
standby automatically when no PLD inputs are changing to conserve power.
The logic configuration (from equations) of both PLDs is stored with non-volatile Flash
technology and the logic is active upon power-up. PLDs may NOT be programmed by the
8032, PLD programming only occurs through the JTAG interface.
Figure 63. Memory page register
Page
Register
8032
Data
Bus
Load or
Read via
csiop +
offset E0h
D0
Q0
D1
Q1
D2
Q2
D3
Q3
D4
Q4
D5
Q5
D6
Q6
D7
Q7
RST
PGR0-7
RST
(PSD Module Reset)
DPLD
and
GPLD
Chip-
Selects
and
General
Logic
AI09172
28.1.9
PLD #1, decode PLD (DPLD)
This programmable logic implements memory mapping and is used to select one of the
individual Main Flash memory segments, one of individual Secondary Flash memory
segments, the SRAM, or the group of csiop registers when the 8032 presents an address to
DPLD inputs (see Figure 75 on page 217). The DPLD can also optionally drive external chip
select signals on Port D pins. The DPLD also optionally produces two select signals (PSEL0
and PSEL1) used to enable a special data bus repeater function on Port A, referred to as
Peripheral I/O Mode. There are 69 DPLD input signals which include: 8032 address and
control signals, Page Register outputs, PSD Module Port pin inputs, and GPLD logic
feedback.
28.1.10
PLD #2, general PLD (GPLD)
This programmable logic is used to create both combinatorial and sequential general
purpose logic (see Figure 76 on page 218). The GPLD contains 16 Output Macrocells
(OMCs) and 20 Input Macrocells (IMCs). Output Macrocell registers are unique in that they
have direct connection to the 8032 data bus allowing them to be loaded and read directly by
the 8032 at runtime through OMC registers in csiop. This direct access is good for making
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