UPSD3422_06 Datasheet, PDF (163/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

uPSD34xx
USB interface
● USB Control Register (UCTL)
The USB Control Register (see Table 80) is used to enable the SIE, make the Endpoint
FIFOs visible in the XDATA space and for generating a remote wakeup signal. Upon a
reset, the USB module is disabled and must be enabled by the CPU for communication
with the host over the USB.
Table 80.
Bit 7
–
USB control register (UCTL 0ECh, reset value 00h)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
–
–
–
–
USBEN
Bit 1
VISIBLE
Bit 0
WAKEUP
Bit
Symbol
R/W
Definition
7
–
–
Reserved
6
–
–
Reserved
5
–
–
Reserved
4
–
–
Reserved
3
–
–
Reserved
USB Enable
When this bit is set, the USB function is enabled and the SIE
responds to tokens from the host. When this bit is clear, the
USB function is disabled and does not respond to any tokens
2
USBEN
R/W from the host.
Note: A USB reset does not clear this bit. Disabling and
enabling the SIE using this bit resets part of the USB SIE state
machine and some of the bits in the USTA and UCON
registers.
USB FIFO VISIBLE
1
VISIBLE
R/W _{When this bit is set, the selected USB FIFO is accessible}
(visible) in the XDATA space.
Remote Wakeup Enable
This bit forces a resume or “K” state on the USB data lines to
0
WAKEUP
R/W ^{initiate a remote wake-up. The CPU is responsible for}
controlling the timing of the forced resume that must be
between 10ms and 15ms. Setting this bit will not cause the
RESUMF Bit to be set.
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