UPSD3422_06 Datasheet, PDF (157/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

uPSD34xx
USB interface
● USB IN FIFO Interrupt Enable Register (UIE1)
When an endpoint’s IN FIFO has been successfully sent to the host with an IN
transaction, the FIFO becomes empty. The UIE1 register is used to enable each
endpoint’s IN FIFO interrupt (Table 73).
● USB OUT FIFO Interrupt Enable Register (UIE1)
When an endpoint’s OUT FIFO has been filled by an OUT transaction from the host,
the FIFO becomes full. The UIE2 register is used to enable each endpoint’s OUT FIFO
interrupt (Table 74).
Table 73.
Bit 7
–
USB IN FIFO interrupt enable register (UIE1 0E5h, reset value 00h)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
–
–
IN4IE
IN3IE
IN2IE
IN1IE
IN0IE
Bit
Symbol
R/W
Definition
7
–
–
Reserved
6
–
–
Reserved
5
–
–
Reserved
4
IN4IE
R/W Enable Endpoint 4 IN FIFO interrupt
3
IN3IE
R/W Enable Endpoint 3 IN FIFO interrupt
2
IN2IE
R/W Enable Endpoint 2 IN FIFO interrupt
1
IN1IE
R/W Enable Endpoint 1 IN FIFO interrupt
0
IN0IE
R/W Enable Endpoint 0 IN FIFO interrupt
Table 74.
Bit 7
–
USB OUT FIFO interrupt enable register (UIE2 0E6h, Reset Value 00h)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
–
–
OUT4IE OUT3IE OUT2IE OUT1IE OUT0IE
Bit
Symbol
R/W
Definition
7
–
–
Reserved
6
–
–
Reserved
5
–
–
Reserved
4
OUT4IE
R/W Enable Endpoint 4 OUT FIFO interrupt
3
OUT3IE
R/W Enable Endpoint 3 OUT FIFO interrupt
2
OUT2IE
R/W Enable Endpoint 2 OUT FIFO interrupt
1
OUT1IE
R/W Enable Endpoint 1 OUT FIFO interrupt
0
OUT0IE
R/W Enable Endpoint 0 OUT FIFO interrupt
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