UPSD3422_06 Datasheet, PDF (244/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

PSD module
uPSD34xx
Table 145. Power management mode register PMMR2 (address = csiop + offset B4h)
Bit 0
X
0 Not used, and should be set to zero.
Bit 1
X
0 Not used, and should be set to zero.
Blocking Bit,
Bit 2
WR to
PLDs⁽¹⁾
Blocking Bit,
Bit 3
RD to
PLDs⁽¹⁾
Blocking Bit,
Bit 4 PSEN to
PLDs⁽¹⁾
Blocking Bit,
Bit 5
ALE to
PLDs⁽¹⁾
Blocking Bit,
Bit 5
PC7 to
PLDs⁽¹⁾
0=
on
8032 WR input to the PLD Input Bus is not blocked.
1=
off
8032 WR input to PLD Input Bus is blocked, saving power.
0=
on
8032 RD input to the PLD Input Bus is not blocked.
1=
off
8032 RD input to PLD Input Bus is blocked, saving power.
0=
on
8032 PSEN input to the PLD Input Bus is not blocked.
1=
off
8032 PSEN input to PLD Input Bus is blocked, saving power.
0=
on
8032 ALE input to the PLD Input Bus is not blocked.
1=
off
8032 ALE input to PLD Input Bus is blocked, saving power.
0=
on
Pin PC7 input to the PLD Input Bus is not blocked.
1=
off
Pin PC7 input to PLD Input Bus is blocked, saving power.
Bit 7
X
0 Not used, and should be set to zero.
Note:
The bits of this register are cleared to zero following Power-up. Subsequent Reset (RST)
pulses do not clear the registers.
Note: 1 Blocking bits should be set to logic ’1’ only if the signal is not needed in a DPLD or GPLD
logic equation.
Table 146. Power Management Mode Register PMMR3 (address = csiop + offset C7h)
Bit 0
X
0 Not used, and should be set to zero.
0=
off
APD counter will cause Power-Down Mode if APD is enabled.
Bit 1 FORCE_PD
1 = Power-Down mode will be entered immediately regardless of APD
on activity.
Bit 3-
7
X
0 Not used, and should be set to zero.
Note:
The bits of this register are cleared to zero following Power-up. Subsequent Reset (RST)
pulses do not clear the registers.
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