UPSD3422_06 Datasheet, PDF (194/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

PSD module
uPSD34xx
28.2.5
Note:
maintained by alternating between the two flash sectors. For example, a data set of 128
bytes is written and maintained by software in a distributed fashion across one 8K byte
sector of Secondary Flash memory until it becomes full. Then the writing continues on the
other 8K byte sector while erasing the first 8K byte sector. This process repeats
continuously, bouncing back and forth between the two 8K byte sectors. This creates a
wear-leveling effect, which increases the effective number of erase cycles for a data set of
128 bytes to many times more than the base 100K erase cycles of the Flash memory.
EEPROM emulation in Flash memory is typically faster than writing to actual EEPROM
memory, and more reliable because the last known value in a data set is maintained even if
a WRITE cycle is corrupted by a power outage. The EEPROM emulation function can be
called by the user’s firmware, making it appear that the user is writing a single byte, or data
record, thus hiding all of the data management that occurs within the two 8K byte flash
sectors. EEPROM emulation firmware for the uPSD34xx is available from www.st.com/psm.
Alternative mapping schemes
Here are more possible memory maps for the uPSD3433.
Mapping examples would be slightly different for uPSD3433 and uPSD3434, because of the
different sizes of individual Flash memory sectors.
● Figure 66 Place the larger Main Flash Memory into program space, but split the
Secondary Flash in half, placing two of its sectors into XDATA space and remaining two
sectors into program space. This method allows the designer to put IAP code (or boot
code) into two sectors of Secondary Flash in program space, and use the other two
Secondary Flash sectors for data storage, such as EEPROM emulation in XDATA
space.
● Figure 67 Place both the Main and Secondary Flash memories into program space for
maximum code storage, with no Flash memory in XDATA space.
Figure 66. Mapping: split second Flash in half
FFFFh
8032 PROGRAM
SPACE (PSEN)
Page Page Page Page
0
1
2
3
8032 XDATA SPACE
(RD and WR)
Page X
FFFFh
fs1 fs3 fs5 fs7
16KB 16KB 16KB 16KB
C000h
8000h
fs0
16KB
fs2
16KB
fs4
16KB
fs6
16KB
Nothing Mapped
4000h
csboot1, 8KB
2000h ^{Common Memory to All Pages}
csboot0, 8KB
0000h ^{Common Memory to All Pages}
System I/O
8000h
csboot3
8KB
6000h
csboot2
8KB _4000h
System I/O _2100h
csiop, 256B _2000h
rs0, 8KB
0000h
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