UPSD3422_06 Datasheet, PDF (78/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

MCU bus interface
18 MCU bus interface
uPSD34xx
The MCU Module has a programmable bus interface which is a modified 8032 bus with 16
multiplexed address and data lines. The bus supports four types of data transfer (16- or 8-
bit), each transfer is to/from a memory location external to the MCU Module:
● Code Fetch cycle using the PSEN signal: fetch a 16-bit code word for filling the pre-
fetch queue. The CPU fetches a code byte from the PFQ for execution;
● Code Read cycle using PSEN: read a 16-bit code word using the MOVC (Move
Constant) instruction. The code word is routed directly to the CPU and by-pass the
PFQ;
● XDATA Read cycle using the RD signal: read a data byte using the MOVX (Move
eXternal) instruction; and
● XDATA Write cycle using the WR signal: write a data byte using the MOVX instruction
18.1
PSEN bus cycles
In a PSEN bus cycle, the MCU module fetches the instruction from the 16-bit program
memory in the PSD module. The multiplexed address/data bus AD[15:0] is connected to the
PSD module for 16-bit data transfer. The uPSD34xx does not support external PSEN cycles
and cannot fetch instruction from other external program memory devices.
18.2
READ or WRITE bus cycles
In an XDATA READ or WRITE bus cycle, the MCU’s multiplexed AD[15:0] bus is connected
to the PSD module, but only the lower bytes AD[7:0] are used for the 8-bit data transfer. The
AD[7:0] lines are also connected to pins in the 80-pin package for accessing external
devices. If the high address byte A[15:8] is needed for external devices, Port B in the PSD
Module can be configured to provide the latched A[15:8] address outputs.
18.3
Connecting external devices to the MCU bus
The uPSD34xx supports 8-bit only external I/O or Data memory devices. The READ and
WRITE data transfer is carried out on the AD[7:0] bus which is available in the 80-pin
package. The address lines can be brought out to the external devices in one of three ways:
1. Configure Ports B and A of the PSD Module in Address Output mode, as shown in
Figure 20;
2. Use Port B together with an external latch, as shown in Figure 21 on page 79. The
external latch latches the low address byte from the AD[7:0] bus with the ALE
signal.This configuration is for design where Port A is needed for CPLD functions; and
3. Configure the microcell in the CPLD to output any address line to any of the CPLD
output pins. This is the most flexible implementation but requires the use of CPLD
resources.
Ports A and B in the PSD Module can be configured in the PSDsoft to provide latched MCU
address A[7:0] and A[15:8] (see Section 28.5: PSD module detailed operation on page 201
for details on how to enable Address Output mode). The latched address outputs on the
ports are pin configurable. For example, Port B pins PB[2:0] can be enabled to provide
78/293