UPSD3422_06 Datasheet, PDF (139/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

uPSD34xx
SPI (synchronous peripheral interface)
16, 20, all the way up to 252. For example, if SPICLKD contains 0x24, SPICLK has the
frequency of PERIH_CLK divided by 36 decimal.
The SPICLK frequency must be set low enough to allow the MCU time to read received data
bytes without loosing data. This is dependent upon many things, including the crystal
frequency of the MCU and the efficiency of the SPI firmware.
24.6
Dynamic control
At runtime, bits in registers SPICON0, SPICON1, and SPISTAT are managed by firmware
for dynamic control over the SPI interface. The bits Transmitter Enable (TE) and Receiver
Enable (RE) when set will allow transmitting and receiving respectively. If TE is disabled,
both transmitting and receiving are disabled because SPICLK is driven to constant output
logic ‘0’ (when SPO = 0) or logic '1' (when SPO = 1).
When the SSEL Bit is set, the SPISEL pin will drive to logic '0' (active) to select a connected
slave device at the appropriate time before the first data bit of a byte is transmitted, and
SPISEL will automatically return to logic '1' (inactive) after transmitting the eight bit of data,
as shown in Figure 47 on page 137. SPISEL will continue to automatically toggle this way
for each byte data transmission while the SSEL bit is set by firmware. When the SSEL Bit is
cleared, the SPISEL pin will drive to constant logic '1' and stay that way (after a transmission
in progress completes).
The Interrupt Enable Bits (TEIE, RORIE,TIE, and RIE) when set, will allow an SPI interrupt
to be generated to the MCU upon the occurrence of the condition enabled by these bits.
Firmware must read the four corresponding flags in the SPISTAT register to determine the
specific cause of interrupt. These flags are automatically cleared when firmware reads the
SPISTAT register.
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