UPSD3422_06 Datasheet, PDF (207/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

uPSD34xx
PSD module
attempted to program bit to logic ’1’ when that bit was already programmed to logic ’0’ (must
erase to achieve logic ’1’).
It is suggested (as with all Flash memories) to read the location again after the embedded
programming algorithm has completed, to compare the byte that was written to the Flash
memory with the byte that was intended to be written.
When using the Data Polling method during an erase operation, Figure 72 still applies.
However, the Data Polling Flag Bit (DQ7) is '0' until the erase operation is complete. A ’1’ on
the Error Flag Bit (DQ5) indicates a time-out condition on the Erase cycle, a ’0’ indicates no
error. The 8032 can read any location within the sector being erased to get the Data Polling
Flag Bit (DQ7) and the Error Flag Bit (DQ5).
Figure 72. Data polling flowchart
START
READ DQ5 & DQ7
at VALID ADDRESS
DQ7
=
YES
DATA
NO
NO _DQ5
=1
YES
READ DQ7
DQ7
=
YES
DATA
NO
FAIL
PASS
AI01369B
28.5.11
Data Toggle
Checking the Toggle Flag Bit (DQ6) is another method of determining whether a program or
erase operation is in progress or has completed. Figure 73 shows the Data Toggle
algorithm.
When the 8032 issues a program instruction sequence, the embedded algorithm within the
Flash memory array begins. The 8032 then reads the location of the byte to be programmed
in Flash memory to check status. The Toggle Flag Bit (DQ6) of this location toggles each
time the 8032 reads this location until the embedded algorithm is complete. The 8032
continues to read this location, checking the Toggle Flag Bit (DQ6) and monitoring the Error
Flag Bit (DQ5). When the Toggle Flag Bit (DQ6) stops toggling (two consecutive reads yield
the same value), then the embedded algorithm is complete. If the Error Flag Bit (DQ5) is '1,'
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