UPSD3422_06 Datasheet, PDF (50/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

Debug unit
12 Debug unit
uPSD34xx
The 8032 MCU Module supports run-time debugging through the JTAG interface. This same
JTAG interface is also used for In-System Programming (ISP) and the physical connections
are described in the PSD Module section, Section 28.6.1: JTAG ISP and JTAG debug on
page 251.
Debugging with a serial interface such as JTAG is a non-intrusive way to gain access to the
internal state of the 8032 MCU core and various memories. A traditional external hardware
emulator cannot be completely effective on the uPSD34xx because of the Pre-Fetch Queue
and Branch Cache. The nature of the PFQ and BC hide the visibility of actual program flow
through traditional external bus connections, thus requiring on-chip serial debugging
instead.
Debugging is supported by Windows PC based software tools used for 8051 code
development from 3rd party vendors listed at www.st.com/psm. Debug capabilities include:
● Halt or Start MCU execution
● Reset the MCU
● Single Step
● 3 Match Breakpoints
● 1 Range Breakpoint (inside or outside range)
● Program Tracing
● Read or Modify MCU core registers, DATA, IDATA, SFR, XDATA, and Code
● External Debug Event Pin, Input or Output
Some key points regarding use of the JTAG Debugger.
– The JTAG Debugger can access MCU registers, data memory, and code memory
while the MCU is executing at full speed by cycle-stealing. This means “watch
windows” may be displayed and periodically updated on the PC during full speed
operation. Registers and data content may also be modified during full speed
operation.
– There is no on-chip storage for Program Trace data, but instead this data is
scanned from the uPSD34xx through the JTAG channel at run-time to the PC host
for proccessing. As such, full speed program tracing is possible only when the
8032 MCU is operating below approximately one MIPS of performance. Above
one MIPS, the program will not run real-time while tracing. One MIPS performance
is determined by the combination of choice for MCU clock frequency, and the bit
settings in SFR registers BUSCON and CCON0.
– Breakpoints can optionally halt the MCU, and/or assert the external Debug Event
pin.
– Breakpoint definitions may be qualified with read or write operations, and may also
be qualified with an address of code, SFR, DATA, IDATA, or XDATA memories.
– Three breakpoints will compare an address, but the fourth breakpoint can
compare an address and also data content. Additionally, the fouth breakpoint can
be logically combined (AND/OR) with any of the other three breakpoints.
– The Debug Event pin can be configured by the PC host to generate an output
pulse for external triggering when a break condition is met. The pin can also be
configured as an event input to the breakpoint logic, causing a break on the falling-
edge of an external event signal. If not used, the Debug Event pin should be pulled
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