UPSD3422_06 Datasheet, PDF (274/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

DC and AC parameters
uPSD34xx
Table 167. CPLD macrocell synchronous clock mode timing (5V PSD module)
Symbol
Parameter
Conditions Min
Max
PT
Aloc
Turbo
Off
Slew
rate⁽¹⁾
Unit
Maximum Frequency
External Feedback
1/(t_S+t_CO)
f_MAX
Maximum Frequency
Internal Feedback (f_CNT)
Maximum Frequency
Pipelined Data
1/(t_S+t_CO–
10)
1/(t_CH+t_CL)
t_S Input Setup Time
12
t_H Input Hold Time
0
t_CH Clock High Time
Clock Input 6
t_CL Clock Low Time
Clock Input 6
t_CO Clock to Output Delay
Clock Input
t_ARD CPLD Array Delay
Any
macrocell
t_MIN Minimum Clock Period⁽²⁾
t_CH+t_CL
12
40.0
66.6
83.3
+2
13
11 + 2
+ 10
MHz
MHz
MHz
ns
ns
ns
ns
– 2 ns
ns
ns
Note: 1 Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by
given amount.
2 CLKIN (PD1) t_CLCL = t_CH + t_CL.
Table 168. CPLD Macrocell Synchronous Clock Mode Timing (3V PSD Module)
Symbol
Parameter
Conditions
Min
Max
PT Turbo Slew
Aloc Off rate⁽¹⁾
Unit
Maximum Frequency
External Feedback
1/(t_S+t_CO)
23.2
MHz
f_MAX
Maximum Frequency
Internal Feedback (f_CNT)
Maximum Frequency
Pipelined Data
1/(t_S+t_CO–10)
1/(t_CH+t_CL)
30.3
40.0
MHz
MHz
t_S Input Setup Time
20
+ 4 + 15
ns
t_H Input Hold Time
0
ns
t_CH Clock High Time
Clock Input 15
ns
t_CL Clock Low Time
Clock Input 10
ns
t_CO Clock to Output Delay
Clock Input
23
– 6 ns
t_ARD CPLD Array Delay
Any macrocell
20 + 4
ns
t_MIN Minimum Clock Period⁽²⁾
t_CH+t_CL
25
ns
Note: 1 Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by
given amount.
2 CLKIN (PD1) t_CLCL = t_CH + t_CL.
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