UPSD3422_06 Datasheet, PDF (117/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

uPSD34xx
I²C interface
A few things to know related to these transfers:
● Either the Master or Slave device can hold the SCL clock line low to indicate it needs
more time to handle a byte transfer. An indefinite holding period is possible.
● A START condition is generated by a Master and recognized by a Slave when SDA has
a 1-to-0 transition while SCL is high (Figure 42 on page 117).
● A STOP condition is generated by a Master and recognized by a Slave when SDA has
a 0-to1 transition while SCL is high (Figure 42 on page 117).
● A RE-START (repeated START) condition generated by a Master can have the same
function as a STOP condition when starting another data transfer immediately following
the previous data transfer (Figure 42 on page 117).
● When transferring data, the logic level on the SDA line must remain stable while SCL is
high, and SDA can change only while SCL is low. However, when not transferring data,
SDA may change state while SCL is high, which creates the START and STOP bus
conditions.
● An Acknowlegde bit is generated from a Master or a Slave by driving SDA low during
the “ninth” bit time, just following each 8-bit byte that is transfered on the bus (Figure 42
on page 117). A Non-Acknowledge occurs when SDA is asserted high during the ninth
bit time. All byte transfers on the I²C bus include a 9th bit time reserved for an
Acknowlege (ACK) or Non-Acknowledge (NACK).
● An additional Master device that desires to control the bus should wait until the bus is
not busy before generating a START condition so that a possible Slave operation is not
interrupted.
● If two Master devices both try to generate a START condition simultaneously, the
Master who looses arbitration will switch immediately to Slave mode so it can
recoginize its own Slave address should it appear on the bus.
Figure 42. Data Transfer on an I²C Bus
7-bit Slave
Address
READ/WRITE
Indicator
MSB
R/W ACK
Acknowledge
bits from
receiver
MSB
NACK
ACK
Stop
Condition
Repeated
Start
Condition
Start
Condition
1
2
3-6
7
8
9
Clock can be held low
to stall transfer.
1
2
3-8
9
Repeated if more
data bytes are
transferred.
AI09625
23.3
Operating modes
The I²C interface supports four operating modes:
● Master-Transmitter
● Master-Receiver
● Slave-Transmitter
● Slave-Receiver
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