UPSD3422_06 Datasheet, PDF (196/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

PSD module
uPSD34xx
28.2.6
Note:
from the Secondary Flash memory in program space. After the writing is complete, the Main
Flash can be “reclassified” back to program space, then execution can continue from the
new code in Main Flash memory. The mapping example of Figure 68 will accommodate this
operation.
Memory sector select rules
When defining sector select signals (FSx, CSBOOTx, RS0, CSIOP, PSELx) in PSDsoft
Express, the user must keep these rules in mind:
● Main Flash and Secondary Flash memory sector select signals may not be larger than
their physical sector size as defined in Table 101 on page 187.
● Any Main Flash memory sector select may not be mapped in the same address range
as another Main Flash sector select (cannot overlap segments of Main Flash on top of
each other).
● Any Secondary Flash memory sector select may not be mapped in the same address
range as another Secondary Flash sector select (cannot overlap segments of
Secondary Flash on top of each other).
● A Secondary Flash memory sector may overlap a Main Flash memory sector. In the
case of overlap, priority is given to the Secondary Flash memory sector.
● SRAM, CSIOP, or PSELx may overlap any Flash memory sector. In the case of overlap,
priority is given to SRAM, CSIOP, or PSELx.
PSELx is for optional Peripheral I/O Mode on Port A.
● The address range for sector selects for SRAM, PSELx, and CSIOP must not overlap
each other as they have the same priority, causing contention if overlapped.
Figure 69 illustrates the priority scheme of the memory elements of the PSD Module.
Priority refers to which memory will ultimately produce a byte of data or code to the 8032
MCU for a given bus cycle. Any memory on a higher level can overlap and has priority over
any memory on a lower level. Memories on the same level must not overlap.
Example: FS0 is valid when the 8032 produces an address in the range of 8000h to BFFFh.
CSBOOT0 is valid from 8000h to 9FFFh. RS0 is valid from 8000h to 87FFh. Any address
from the 8032 in the range of RS0 always accesses the SRAM. Any address in the range of
CSBOOT0 greater than 87FFh (and less than 9FFFh) automatically addresses Secondary
Flash memory. Any address greater than 9FFFh accesses Main Flash memory. One-half of
the Main Flash memory segment and one-fourth of the Secondary Flash memory segment
cannot be accessed by the 8032.
Figure 69. PSD module memory priority
Highest Priority
Level 1
SRAM,
CSIOP, and
Peripheral I/O
Mode
Level 2
Secondary
Flash Memory
Level 3
Main Flash Memory
Lowest Priority
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