UPSD3422_06 Datasheet, PDF (62/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

MCU clock generation
uPSD34xx
Table 22.
Bit 7
PLLM[4]
CCON0: Clock Control Register (SFR F9h, reset value 50h)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PLLEN UPLLCE DBGCE CPUAR
CPUPS[2:0]
Bit 0
Bit
Symbol
R/W
Definition
7
PLLM[4]
R,W
Upper bit of the 5-bit PLLM[4:0] Multiplier (Default: '0' for
PLLM = 00h)
PLL Enable
6
PLLEN
R,W 0 = Disable PLL operation
1 = Enable PLL operation (Default condition after reset)
USB Clock Enable
5
UPLLCE
R,W 0 = USB clock is disabled (Default condition after reset)
1 = USB clock is enabled
Debug Unit Breakpoint Comparator Enable
4
DBGCE
R,W _{0 = JTAG Debug Unit comparators are disabled}
1 = JTAG Debug Unit comparators are enabled (Default
condition after reset)
Automatic MCU Clock Recovery
3
CPUAR
R,W ^{0 = There is no change of CPUPS[2:0] when an interrupt}
occurs.
1 = Contents of CPUPS[2:0] automatically become 000b
whenever any interrupt occurs.
MCUCLK Pre-Scaler
2:0
Table 23.
Bit 7
CPUPS
R,W
000b: f_MCU = f_OSC (Default after reset)
001b: f_MCU = f_OSC/2
010b: f_MCU = f_OSC/4
011b: f_MCU = f_OSC/8
100b: f_MCU = f_OSC/16
101b: f_MCU = f_OSC/32
110b: f_MCU = f_OSC/1024
111b: f_MCU = f_OSC/2048
CCON1 PLL Control Register (SFR FAh, reset value 00h)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PLLM[3:0]
PLLD[3:0]
Bit 0
Bit
Symbol
R/W
Definition
Lower 4 bits of the 5-bit PLLM[4:0] Multiplier (Default after
7:4
PLLM[3:0] R,W ^{reset: PLLM = 00h)}
PLLM[4] is in the CCON0 Register.
3:0
PLLD[3:0] R,W 4-bit PLL Divider (Default after reset: PLLD = 0h)
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