UPSD3422_06 Datasheet, PDF (273/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

uPSD34xx
DC and AC parameters
Symbol
Parameter
t_ARPW
CPLD Register Clear or
Preset Pulse Width
t_ARD CPLD Array Delay
Conditions Min
PT Turbo Slew
Max
Aloc
Off
rate^{(1) Unit}
10
+ 10
ns
Any
macrocell
11 + 2
ns
Note: 1 Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by
given amount
2 t_PD for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR,
PSEN and ALE to CPLD combinatorial output (80-pin package only)
Table 166. CPLD combinatorial timing (3V PSD module)
Symbol
Parameter
Conditions Min Max
PT
Aloc
Turbo
Off
Slew
rate⁽¹⁾
Unit
t_PD(2)
CPLD Input Pin/Feedback
to CPLD Combinatorial
Output
35 + 4 + 15 – 6 ns
t_EA
CPLD Input to CPLD
Output Enable
t_ER
CPLD Input to CPLD
Output Disable
CPLD Register Clear or
t_{ARP Preset Delay}
38
+ 15 – 6 ns
38
+ 15 – 6 ns
35
+ 15 – 6 ns
CPLD Register Clear or
t_{ARPW Preset Pulse Width}
18
+ 15
ns
t_ARD CPLD Array Delay
Any
macrocell
20 + 4
ns
Note: 1 Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by
given amount
2 t_PD for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR,
PSEN and ALE to CPLD combinatorial output (80-pin package only)
Figure 102. Synchronous Clock Mode Timing – PLD
tCH
tCL
CLKIN
INPUT
REGISTERED
OUTPUT
tS
tH
tCO
AI02860
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