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UPSD3422_06 Datasheet, PDF (102/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic
Serial UART interfaces
uPSD34xx
Table 48.
Bit 7
SM0
SCON1: serial port UART1 control register (SFR D8h, reset value 00h)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SM1
SM2
REN
TB8
RB8
TI
RI
Bit
Symbol
R/W
Definition
7
SM0
R,W Serial Mode Select, See Table 46 on page 100.
Important, notice bit order of SM0 and SM1.
[SM0:SM1] = 00b, Mode 0
6
SM1
R,W [SM0:SM1] = 01b, Mode 1
[SM0:SM1] = 10b, Mode 2
[SM0:SM1] = 11b, Mode 3
Serial Multiprocessor Communication Enable.
Mode 0: SM2 has no effect but should remain 0.
5
SM2
R,W Mode 1: If SM2 = 0 then stop bit ignored. SM2 =1 then RI
active if stop bit = 1.
Mode 2 and 3: Multiprocessor Comm Enable. If SM2=0, 9th
bit is ignored. If SM2=1, RI active when 9th bit = 1.
Receive Enable.
4
REN
R,W If REN=0, UART reception disabled. If REN=1, reception is
enabled
3
TB8
R,W
TB8 is assigned to the 9th transmission bit in Mode 2 and 3.
Not used in Mode 0 and 1.
Mode 0: RB8 is not used.
Mode 1: If SM2 = 0, the RB8 is the level of the received stop
2
RB8
R,W bit.
Mode 2 and 3: RB8 is the 9th data bit that was received in
Mode 2 and 3.
Transmit Interrupt flag.
1
TI
R,W Causes interrupt at end of 8th bit time when transmitting in
Mode 0, or at beginning of stop bit transmission in other
modes. Must clear flag with firmware.
Receive Interrupt flag.
0
RI
R,W Causes interrupt at end of 8th bit time when receiving in Mode
0, or halfway through stop bit reception in other modes (see
SM2 for exception). Must clear this flag with firmware.
21.3
UART baud rates
The baud rate in Mode 0 is fixed:
Mode 0 Baud Rate = fOSC / 12
The baud rate in Mode 2 depends on the value of the bit SMOD in the SFR named PCON. If
SMOD = 0 (default value), the baud rate is 1/64 the oscillator frequency, fOSC. If SMOD = 1,
the baud rate is 1/32 the oscillator frequency.
Mode 2 Baud Rate = (2SMOD / 64) x fOSC
Baud rates in Modes 1 and 3 are determined by the Timer 1 or Timer 2 overflow rate.
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