UPSD3422_06 Datasheet, PDF (121/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

uPSD34xx
I²C interface
23.8 I²C interface control register (S1CON)
Table 54.
Bit 7
CR2
Serial control register S1CON (SFR DCh, reset value 00h)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ENI1
STA
STO
ADDR
AA
CR[1:0]
Bit
Symbol
R/W
Function
This bit, along with bits CR1 and CR0, determine the SCL
7
CR2
R,W clock frequency (f_SCL) when SIOE is in Master mode. These
bits create a clock divisor for f_OSC. See Table 55.
I²C Interface Enable
6
ENI1
R,W _{0 = SIOE disabled, 1 = SIOE enabled. When disabled, both}
SDA and SCL signals are in high impedance state.
START flag.
When set, Master mode is entered and SIOE generates a
START condition only if the I²C bus is not busy. When a
5
STA
R,W _{START condition is detected on the bus, the STA flag is}
cleared by hardware. When the STA bit is set during an
interrupt service, the START condition will be generated after
the interrupt service.
STOP flag
When STO is set in Master mode, the SIOE generates a
4
STO
R,W ^{STOP condition. When a STOP condition is detected, the STO}
flag is cleared by hardware. When the STO bit is set during an
interrupt service, the STOP condition will be generated after
the interrupt service.
This bit is set when an address byte received in Slave mode
3
ADDR
R,W matches the device address programmed into the S1ADR
register. The ADDR bit must be cleared with firmware.
Assert Acknowledge enable
If AA = 1, an acknowledge signal (low on SDA) is automatically
returned during the acknowledge bit-time on the SCL line
when any of the following three events occur:
1. SIOE in Slave mode receives an address that
matches contents of S1ADR register
2
AA
R,W _{2. A data byte has been received while SIOE is in}
Master Receiver mode
3. A data byte has been received while SIOE is a
selected Slave Receiver
When AA = 0, no acknowledge is returned (high on SDA
during acknowledge bit-time).
These bits, along with bit CR2, determine the SCL clock
1, 0
CR1, CR0
R,W frequency (f_SCL) when SIOE is in Master mode. These bits
create a clock divisor for f_OSC. See Table 55 for values.
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