UPSD3422_06 Datasheet, PDF (142/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

SPI (synchronous peripheral interface)
uPSD34xx
Table 66.
Bit 7
–
SPISTAT: SPI interface status register (SFR D3h, reset value 02h)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
–
–
BUSY
TEISF RORISF
TISF
RISF
Bit
Symbol
R/W
Definition
7-5
–
4
BUSY
3
TEISF
2
RORISF
1
TISF
0
RISF
–
Reserved
SPI Busy
R
0 = Transmit or Receive is completed
1 = Transmit or Receive is in process
Transmission End Interrupt Source flag
R
0 = Automatically resets to '0' when firmware reads this
register
1 = Automatically sets to '1' when transmission end occurs
Receive Overrun Interrupt Source flag
R
0 = Automatically resets to '0' when firmware reads this
register
1 = Automatically sets to '1' when receive overrun occurs
Transfer Interrupt Source flag
0 = Automatically resets to '0' when SPITDR is full (just after
R
the SPITDR is written)
1 = Automatically sets to '1' when SPITDR is empty (just after
byte loads from SPITDR into SPI shift register)
Receive Interrupt Source flag
R
0 = Automatically resets to '0' when SPIRDR is empty (after
the SPIRDR is read)
1 = Automatically sets to '1' when SPIRDR is full
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