UPSD3422_06 Datasheet, PDF (60/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

MCU clock generation
uPSD34xx
14.2.2
USB_CLK
The uPSD34xx has a dedicated analog phase locked loop (PLL) that can be configured to
generate the 48MHz USB_CLK clock on a wide range of f_OSC frequencies. The USB_CLK
must be at 48MHz for the USB to function properly.
The PLL is enabled after power up. The power on lock time for the PLL clock is about 200µs,
and the firmware should wait that much time before enabling the USB_CLK by setting the
UPLLCE Bit in the CCON0 Register to '1.' The PLL is disabled in Power-down mode, it can
also be disabled or enabled by writing to the PLLEN Bit in the CCON0 Register.
The PLL output clock frequency (f_{USB_CLK}) can be determined by using the following
formula:
f_USBCLK = [f_OSC × (PLLM + 2)] ⁄
[(PLLD + 2) × 2]
where PLLM and PLLD are the multiplier and divisor that are specified in the CCON1
Register. The f_OSC, the PLLM and PLLD range must meet the following conditions to
generate a stable USB_CLK:
a) –1 ≤ PLLM ≤ 30 (binary: [11111] ≤ PLLM[4:0] ≤ [11110]),
b) –1 ≤ PLLD ≤ 14 (binary: [1111] ≤ PLLD[3:0] ≤ [1110]), and
c) f_OSC/(PLLD+2) must be equal to or greater than 3MHz.
The USB requires a 48MHz clock to operate correctly. The PLLM[4:0] and PLLD[3:0] values
must be selected so as to generate a USB_CLK that is as close to 48MHz as possible at
different oscillator frequencies (f_OSC). Table 21 lists some of the PLLM and PLLD values that
can be used on common f_OSC frequencies.
Table 21.
f_OSC
(MHz)
PLLM and PLLD Values for Different f_OSC Frequencies
PLLM[4:0]
PLLD[3:0]
decimal
binary
decimal
binary
40.0
22
10110
8
1000
36.0
6
00110
1
0001
33.0
30
11110
9
1001
30.0
14
01110
3
0011
24.0
18
10010
3
0011
16.0
28
11100
3
0011
12.0
30
11110
2
0010
8.0
22
10110
0
0000
6.0
30
11110
0
0000
3.0
30
11110
–1
1111
f_{USB_CLK}
(MHz)
48.0
48.0
48.0
48.0
48.0
48.0
48.0
48.0
48.0
48.0
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