UPSD3422_06 Datasheet, PDF (167/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

uPSD34xx
USB interface
Bit Symbol R/W
Definition
FIFO Busy Status
– Endpoint IN Case
Once the FIFO has been loaded and armed (USIZE written with the
number of bytes to send), the BSY Bit is set and remains set until the
SIE has transmitted the data in the FIFO. The CPU should only access
0
BSY R/W the FIFO when BSY = 0.
– Endpoint OUT Case
While the SIE is receiving data and storing it in the FIFO (BSY = 1), it
should not be accessed by the CPU. Once the OUT transaction is
complete (BSY=0), the CPU may read the contents of the FIFO. The
BSY Bit will remain cleared until another OUT transaction is received.
● USB FIFO Valid Size (USIZE)
The Endpoint selected by the USB Endpoint Select Register (see Table 82 on
page 165) determines the direction and FIFO that is controlled by the USB FIFO Valid
Size (see Table 84). The USB FIFO Valid Size Register indicates the number of bytes
loaded into the IN FIFO that the SIE is to send in a Data packet for an Endpoint IN case
and indicates the number of bytes received for an Endpoint OUT case.
Table 84.
Bit 7
–
USB FIFO valid size (USIZE 0F2h, reset value 00h)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
SIZE[6:0]
Bit 1
Bit 0
Bit
Symbol
R/W
Definition
7
–
–
Reserved
– Endpoint IN Case
The CPU writes the USIZE register with the number of bytes it
loaded into the IN endpoint FIFO for transmission with the next
IN transaction. Once the USIZE register has been written, the
FIFO becomes ready for transmission.
6:0
SIZE
R/W ^{– Endpoint OUT Case}
The CPU reads the USIZE register to determine how many
bytes were received in the data packet during the last OUT
transaction. This tells the CPU how many valid bytes to read
from the FIFO.
Note: Since the FIFOs are 64 bytes in length, the maximum
value for SIZE is 64 (40h).
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