UPSD3422_06 Datasheet, PDF (122/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

I²C interface
uPSD34xx
Table 55.
CR2
0
0
0
0
1
1
1
1
Selection of the SCL Frequency in Master Mode based on f_OSC Examples
CR1
CR0
f_OSC
Divided
by:
12MHz
f_OSC
Bit Rate (kHz) @ f_OSC
24MHz
f_OSC
36MHz
f_OSC
40MHz
f_OSC
0
0
32
375
750
X⁽¹⁾
X⁽¹⁾
0
1
48
250
500
750
833
1
0
60
200
400
600
666
1
1
120
100
200
300
333
0
0
240
50
100
150
166
0
1
480
25
50
75
83
1
0
960
12.5
25
37.5
41
1
1
1920
6.25
12.5
18.75
20
Note: 1 These values are beyond the bit rate supported by uPSD34xx.
23.9
23.9.1
I²C interface status register (S1STA)
The S1STA register provides status regarding immediate activity and the current state of
operation on the I²C bus. All bits in this register are read-only except bit 5, INTR, which is
the interrupt flag.
Interrupt conditions
If the I²C interrupt is enabled (EI²C = 1 in SFR named IEA, and EA =1 in SFR named IE),
and the SIOE is initialized, then an interrupt is automatically generated when any one of the
following five events occur:
● When the SIOE receives an address that matches the contents of the SFR, S1ADR.
Requirements: SIOE is in Slave Mode, and bit AA = 1 in the SFR S1CON.
● When the SIOE receives General Call address. Requirments: SIOE is in Slave Mode,
bit AA = 1 in the SFR S1CON
● When a complete data byte has been received or transmitted by the SIOE while in
Master mode. The interrupt will occur even if the Master looses arbitration.
● When a complete data byte has been received or transmitted by the SIOE while in
selected Slave mode.
● A STOP condition on the bus has been recognized by the SIOE while in selected Slave
mode.
Selected Slave mode means the device address sent by the Master device at the beginning
of the current data transfer matched the address stored in the S1ADR register.
If the I²C interrupt is not enabled, the MCU may poll the INTR flag in S1STA.
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