UPSD3422_06 Datasheet, PDF (118/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

I²C interface
uPSD34xx
The interface may operate as either a Master or a Slave within a given application,
controlled by firmware writing to SFRs.
By default after a reset, the I²C interface is in Master Receiver mode, and the SDA/P3.6 and
SCL/P3.7 pins default to GPIO input mode, high impedance, so there is no I²C bus
interference. Before using the I²C interface, it must be initialized by firmware, and the pins
must be configured. This is discussed in Section 23.13: I²C operating sequences on
page 127.
23.4
Bus arbitration
A Master device always samples the I²C bus to ensure a bus line is high whenever that
Master is asserting a logic 1. If the line is low at that time, the Master recognizes another
device is overriding its own transmission.
A Master may start a transfer only if the I²C bus is not busy. However, it is possible that two
or more Masters may generate a START condition simultaneously. In this case, arbitration
takes place on the SDA line each time SCL is high. The Master that first senses that its bus
sample does not correspond to what it is driving (SDA line is low while it is asserting a high)
will immediately change from Master-Transmitter to Slave-Receiver mode. The arbitration
process can carry on for many bit times if both Masters are addressing the same Slave
device, and will continue into the data bits if both Masters are trying to be Master-
Transmitter. It is also possible for arbitration to carry on into the acknowledge bits if both
Masters are trying to be Master-Receiver. Because address and data information on the bus
is determined by the winning Master, no information is lost during the arbitration process.
23.5
23.5.1
23.5.2
Clock synchronization
Clock synchronization is used to synchronize arbitrating Masters, or used as a handshake
by a devices to slow down the data transfer.
Clock sync during arbitration
During bus arbitration between competing Masters, Master_X, with the longest low period
on SCL, will force Master_Y to wait until Master_X finishes its low period before Master_Y
proceeds to assert its high period on SCL. At this point, both Masters begin asserting their
high period on SCL simultaneously, and the Master with the shortest high period will be the
first to drive SCL for the next low period. In this scheme, the Master with the longest low
SCL period paces low times, and the Master with the shortest high SCL period paces the
high times, making synchronized arbitration possible.
Clock sync during handshaking
This allows receivers in different devices to handle various transfer rates, either at the byte-
level, or bit-level.
At the byte-level, a device may pause the transfer between bytes by holding SCL low to have
time to store the latest received byte or fetch the next byte to transmit.
At the bit-level, a Slave device may extend the low period of SCL by holding it low. Thus the
speed of any Master device will adapt to the internal operation of the Slave.
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