HD64F3644PV Datasheet, PDF (97/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 3 Exception Handling
SP – 4
SP – 3
SP – 2
SP – 1
SP (R7)
Stack area
SP (R7)
SP + 1
SP + 2
SP + 3
SP + 4
CCR
CCR
PC_H
PC_L
Even address
Prior to start of interrupt
exception handling
PC and CCR
saved to stack
Legend:
PC_H: Upper 8 bits of program counter (PC)
PC_L: Lower 8 bits of program counter (PC)
CCR: Condition code register
SP: Stack pointer
After completion of interrupt
exception handling
Notes: 1. PC shows the address of the first instruction to be executed upon return from the interrupt
handling routine.
2. Register contents must always be saved and restored by word access, starting from
an even-numbered address.
Figure 3.4 Stack State after Completion of Interrupt Exception Handling
Figure 3.5 shows a typical interrupt sequence where the program area is in the on-chip ROM and
the stack area is in the on-chip RAM.
Rev. 6.00 Sep 12, 2006 page 75 of 526
REJ09B0326-0600