HD64F3644PV Datasheet, PDF (83/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 3 Exception Handling
Reset by Watchdog Timer: The watchdog timer counter (TCW) starts counting up when the
WDON bit is set to 1 in the watchdog timer control/status register (TCSRW). If TCW overflows,
the WRST bit is set to 1 in TCSRW and the chip enters the reset state. While the WRST bit is set
to 1 in TCSRW, when TCW overflows the reset state is cleared and reset exception handling
begins. The same reset exception handling is carried out as for input at the RES pin. For details on
the watchdog timer, see section 9.6, Watchdog Timer.
3.2.3 Interrupt Immediately after Reset
After a reset, if an interrupt were to be accepted before the stack pointer (SP: R7) was initialized,
PC and CCR would not be pushed onto the stack correctly, resulting in program runaway. To
prevent this, immediately after reset exception handling all interrupts are masked. For this reason,
the initial program instruction is always executed immediately after a reset. This instruction should
initialize the stack pointer (e.g. MOV.W #xx: 16, SP).
3.3 Interrupts
3.3.1 Overview
The interrupt sources include 12 external interrupts (IRQ₃ to IRQ₀, INT₇ to INT₀) and 21 internal
interrupts from on-chip peripheral modules. Table 3.2 shows the interrupt sources, their priorities,
and their vector addresses. When more than one interrupt is requested, the interrupt with the
highest priority is processed.
The interrupts have the following features:
• Internal and external interrupts can be masked by the I bit in CCR. When the I bit is set to 1,
interrupt request flags can be set but the interrupts are not accepted.
• IRQ₃ to IRQ₀ and INT₇ to INT₀ can be set independently to either rising edge sensing or falling
edge sensing.
Rev. 6.00 Sep 12, 2006 page 61 of 526
REJ09B0326-0600