HD64F3644PV Datasheet, PDF (454/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix A CPU Instruction Set
Mnemonic
Operation
Addressing Mode/
Instruction Length (Bytes)
Condition Code
JSR @@aa:8
RTS
RTE
— SP–2 → SP
PC → @SP
PC ← @aa:8
— PC ← @SP
SP+2 → SP
— CCR ← @SP
SP+2 → SP
PC ← @SP
SP+2 → SP
I HNZVC
2 —————— 8
2 —————— 8
2
10
SLEEP
— Transit to sleep mode.
2 —————— 2
LDC #xx:8, CCR
LDC Rs, CCR
STC CCR, Rd
ANDC #xx:8, CCR
ORC #xx:8, CCR
XORC #xx:8, CCR
NOP
EEPMOV
B #xx:8 → CCR
B Rs8 → CCR
B CCR → Rd8
B CCR∧#xx:8 → CCR
B CCR∨#xx:8 → CCR
B CCR⊕#xx:8 → CCR
— PC ← PC+2
— if R4L≠0
Repeat @R5 → @R6
R5+1 → R5
R6+1 → R6
R4L–1 → R4L
Until R4L=0
else next;
2
2
2
2
2
2
2
2
—————— 2
2
2
2
2 —————— 2
4 —————— 4
Notes: (1) Set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0.
(2) If the result is zero, the previous value of the flag is retained; otherwise the flag is
cleared to 0.
(3) Set to 1 if decimal adjustment produces a carry; otherwise retains value prior to
arithmetic operation.
(4) The number of states required for execution is 4n + 9 (n = value of R4L).
(5) Set to 1 if the divisor is negative; otherwise cleared to 0.
(6) Set to 1 if the divisor is zero; otherwise cleared to 0.
Rev. 6.00 Sep 12, 2006 page 432 of 526
REJ09B0326-0600