HD64F3644PV Datasheet, PDF (281/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 Timers
Input Capture Timing
• Input capture timing
The rising or falling edge is selected for input capture by bits IEDGA to IEDGD in TCRX.
Figure 9.24 shows the timing when the rising edge is selected (IEDGA/B/C/D = 1).
φ
Input capture
pin
Input capture
signal
Figure 9.24 Input Capture Signal Timing (Normal Case)
If the input at the input capture pin occurs while the upper byte of the corresponding input
capture register (ICRA to ICRD) is being read, the internal input capture signal is delayed by
one system clock (φ). Figure 9.25 shows the timing.
ICRA to ICRD upper byte read cycle
T₁
T₂
T₃
φ
Input capture
pin
Input capture
signal
Figure 9.25 Input Capture Signal Timing (during ICRA to ICRD Read)
Rev. 6.00 Sep 12, 2006 page 259 of 526
REJ09B0326-0600