HD64F3644PV Datasheet, PDF (51/551 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 2 CPU
2.5 Instruction Set
The H8/300L Series can use a total of 55 instructions, which are grouped by function in table 2.3.
Table 2.3 Instruction Set
Function
Data transfer
Instructions
MOV, PUSH^*1, POP^*1
Number
1
Arithmetic operations
ADD, SUB, ADDX, SUBX, INC, DEC, ADDS,
14
SUBS, DAA, DAS, MULXU, DIVXU, CMP, NEG
Logic operations
AND, OR, XOR, NOT
4
Shift
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR,
8
ROTXL, ROTXR
Bit manipulation
Branch
BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR,
14
BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST
Bcc^*2, JMP, BSR, JSR, RTS
5
System control
RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP
8
Block data transfer
EEPMOV
1
Total: 55
Notes: 1. PUSH Rn is equivalent to MOV.W Rn, @–SP.
POP Rn is equivalent to MOV.W @SP+, Rn.
2. Bcc is a conditional branch instruction. The same applies to machine language.
Tables 2.4 to 2.11 show the function of each instruction. The notation used is defined next.
Rev. 6.00 Sep 12, 2006 page 29 of 526
REJ09B0326-0600